JPH0341565A - Method for verifying function of logical circuit - Google Patents

Abstract

PURPOSE:To easily grasp an unverified state after executing simulation by inspecting whether a state requiring verification is generated in the simulation or not and displaying the unverified state after ending the simulation. CONSTITUTION:The function of a logical circuit is described by using function symbols stored in an inspection item registered function symbol library and registered in a function description registering means 12. A verification executing state storing means 15 sets up verification executing state flags for respective verification items to the OFF states and stores the set flags, and when a state requiring verification is generated, a verification executing state testing means 14 sets up a verification executing state flag to ON. An unverified item display means 16 verifys the verification executing state flag stored in the means 15 and displays the verification item whose verification executing state flag is ON. Consequently, the unverified state can easily be grasped.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a method for verifying the function of a logic circuit using a simulator, and in particular, in Ja function verification, whether or not all of the verification items to be functionally verified have been verified. This is a functional verification method for a logic circuit that can easily determine whether or not the function has been verified, and if there is a verification item that has not been verified among the verification items that should be functionally verified, the unverified content can be easily grasped.

BACKGROUND OF THE INVENTION In recent years, functional verification methods for logic circuits have been developed to describe the functions of logic circuits using a graphical language that graphically expresses the connections between logic elements or functional elements, or a high-level language called a hardware description language. This is done in a way that a simulation is executed by inputting a verification button into the above description, and the pass/fail of the functional verification result is determined based on whether the output value of the simulation matches the expected value. It is.

Problems to be Solved by the Invention However, with the above method, it is not easy to judge whether all the contents of the input verification button or logic circuit functions that should be verified are verified. Even if some of the content has not been verified, the problem is that if the human output relationship is as expected, a misunderstanding may occur, such as thinking that all the logic circuits are functionally designed correctly. are doing.

In view of the above problems, the present invention describes the function of a logic circuit using a function symbol in which a state to be verified is registered in advance when describing the function of a logic circuit, and when the state to be verified occurs during simulation. By checking whether or not the verification button used in the simulation and displaying unverified states among the states that should be verified after the simulation ends, it is easy to determine whether all of the verification buttons used in the simulation and the states that should be verified have been verified. The purpose of the present invention is to provide a method for verifying the function of a logic circuit, which can easily identify unverified parts and unverified states.

Means for Solving the Problems In order to solve the above problems, the present invention provides a method for verifying functions of a logic circuit that includes a simulator, in which a state to be verified is registered as a preliminary verification item. a function symbol library with verification items registered in which function symbols are registered; a function description registration means for describing and registering the function of a logic circuit using the function symbols in the function symbol library with verification items registered;
When a registered state to be verified occurs during execution of one revolution, a verification execution state check means that turns on a verification execution state flag set for each state, and a verification means that stores the state of the verification execution state flag. Execution state storage means;
and unverified item display means for displaying verification items for which the verification execution state flag of the verification execution state storage means is off after the simulation ends.

Operation With the above-described configuration, the present invention first describes the function of a logic circuit using function symbols in a verification item registered functional symbol library in which functional symbols whose states to be verified are registered in advance as verification items are registered. Register in the function description registration means. The verification execution state storage means sets and stores the verification execution state flag, which is set to the on state when a state corresponding to the item occurs for each verification item, to the off state, and stores the function description in the function description registration means. Input into the simulator and run the simulation.

The verification execution state checking means inputs the state of the functional symbol from the simulator, compares the state of the functional symbol with the state to be verified for the functional symbol, and turns on the verification execution state flag when a state to be verified occurs. ,
The state of the verification execution state flag is stored in the verification execution state storage means. The unverified item display means checks the verification execution state flag stored in the verification execution state storage means, and displays verification items whose verification execution state flags are off, thereby verifying whether the verification button used in the simulation is correct or not. It is possible to easily determine whether or not all states have been verified, and it is also possible to easily grasp unverified states.

Embodiment Hereinafter, a method for verifying the function of a logic circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a method for verifying functions of a logic circuit according to a first embodiment of the present invention.

In FIG. 1, reference numeral 11 indicates a verification item registered functional symbol library in which functional symbols whose states to be verified are registered in advance as verification items are registered, and 12 indicates a verification item registered functional symbol library in which functions of the logic circuit to be verified are registered. 13 is a simulator that inputs the functional description and executes the simulation; 14 is a state to be verified for any functional symbol registered in the verification item registration means;
Compare the state of the corresponding function symbol during simulation execution to check whether a state to be verified has occurred, and if a state to be verified has occurred, set the verification execution state flag set for each state to on. 15 is a verification execution state storage means for storing the state of the verification execution state flag; 16 is a verification execution state storage means for displaying the verification items for which the verification execution state flag of the verification execution state storage means is OFF after the simulation is finished; This is a verification item display means.

The functional verification method for the logic circuit configured as described above will be explained below in Figs. 1, 2, 3, 4, and 5.
The operation will be explained using FIGS. 6 and 7.

First, FIG. 2 shows an example of registering a function description in the function description registration means 12. 31.33 is a flip-flop, 3
2 is an adder, and 34 is a constant multiplier. The functions of the logic circuit are described and registered in a graphical language using functional symbols in the verification item registered functional symbol library II. FIG. 3 shows a verification item for symbol 1 in FIG. 2 as an example of a verification item that is registered.

The description defining the states to be verified registered as shown in FIG. A verification execution state flag is provided which is set to an on state when the verification execution state flag occurs, and the state of the verification execution state flag is set to off as an initial state and is stored. For example, the third
The initial state of the verification execution state storage means 15 for the figure is as shown in FIG.

The functional description registered in the functional description registration means 12 as shown in FIG. 2 is input to the simulator 13, and a simulation is executed. The verification execution state checking means 14 sequentially fetches the state of the functional symbol at the time of simulation execution from the simulator, and compares it with verification items for which the verification execution state flag is off to detect whether a state to be verified has occurred.

When a state to be verified occurs, the corresponding verification execution state flag is set on, and the state of the verification execution state flag is stored in the verification execution state storage means 15.

For example, regarding the operation of the malfunction detection means 14 when executing the simulation for FIG. 3, since all the verification execution state flags are off in the initial state, it is compared with all the states in FIG. 3, and those that match are detected. Set the verification execution status flag to on. The verification execution state storage means 15 stores a verification execution state flag. For example, from the initial state 1
When the TER1 and TER2 events occur, TER
1 is 11 When TER2 is 0 Verification execution state storage means 15
The state is as shown in FIG.

When the next TER1 and TER2 events occur, TER
The states of TER1 and TER2 are checked and compared with the state in which the verification execution state flag in FIG. 5 is OFF, and if they match, the verification execution state flag is set to ON. The verification execution state storage means 15 stores the state of the verification execution state flag. After the simulation ends, the unverified item display means 16 checks the state of the verification execution state flag stored in the verification execution state storage means 15 and displays the verification items for which the verification execution state flag is off. For example, if the state of the verification execution state storage means 15 at the end of the verification is as shown in FIG. 6, the unverified item display means 1
6, it is displayed as shown in FIG.

Such operations are performed for all symbols registered in the functional description registration means 12.

As described above, according to the first embodiment of the present invention, by describing the function of the logic circuit to be verified using the functional symbols in the verification item registered functional symbol library, the state to be verified during simulation execution can be determined. All functional symbols are checked to see if the occurrence has occurred, and the unverified states are displayed by the input button after the simulation is executed, so it is easy to understand the unverified states after the simulation is executed.

Hereinafter, a method for verifying the function of a logic circuit according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 8 is a block diagram of a method for verifying functions of a logic circuit according to a second embodiment of the present invention.

In FIG. 8, reference numeral 21 denotes a verification item registered functional symbol library 22 that stores a group of functional symbols in which states to be verified are registered in advance as verification items.
23 is a function description registration means for describing and registering the function of the logic circuit to be verified using function symbols in a function symbol library with verification item registration; 23 is a simulator for inputting the function description and executing a simulation; 24 is a verification item registration means The state to be verified for any functional symbol registered in is compared with the state of the corresponding functional symbol at the time of simulation execution to verify whether the state to be verified has occurred, and if the state to be verified has occurred. , verification execution state checking means for setting on a verification execution state flag that is set for each state; 25, verification execution state storage means for storing the state of the verification execution state flag; 26, verification execution state storage means for storing the state of the verification execution state flag after the simulation ends. This is an unverified item display means for displaying verification items whose verification execution status flags are off, and the configuration described above is similar to that of FIG. 1. 1st
The configuration differs from the one shown in the figure in that a verification execution state inspection range designating means 27 is provided for designating a functional symbol whose verification state is to be tested among the verification item registered functional symbols written in the functional description registration means.

The operation of the method for verifying the function of the logic circuit configured as described above will be described below with reference to FIGS. 8, 9, and 10.

First, FIG. 9 shows an example of registering a function description in the function description registration means 22. 31.33 is a flip-flop, 32
is an adder, and 34 is a constant multiplier. Functions of logic circuits are described and registered in a graphical language using functional symbols in the verification item registered functional symbol library 21. FIG. 1O shows an example of designation of the verification execution state inspection range designation means 27 for the function description registration means 22, in which symbol 1 in FIG. 9 is designated. The configuration in Figure 10 is
Same as figure.

As shown in FIG. 10, the description that defines the states to be verified only for the designated symbol surrounded by the dotted line is input to the verification execution state storage means 25, and the verification execution state storage means 25 stores each state to be verified. A verification execution state flag is provided which is set to an on state when a state to be verified occurs, and the state of the verification execution state flag is set to off as an initial state and is stored. The functional description registered in the functional description registration means 22 as shown in FIG. 9 is input to the simulator 23 and a simulation is executed. The verification execution state checking means 24 sequentially fetches the state of the functional symbol at the time of simulation execution from the simulator, compares it with the state to be verified, and detects whether the state to be verified has occurred. When a state to be verified occurs, the corresponding verification execution state flag is turned on and the state of the verification execution state flag is stored in the verification execution state storage means 25. After the simulation ends, the unverified item display means 26 checks the state of the verification execution state flag stored in the verification execution state storage means 25 and displays the verification items for which the verification execution state flag is off.

As described above, according to the second embodiment of the present invention, the function of the logic circuit to be verified is described using the function symbol in the function symbol library with verification item registration, and the state to be verified in the function description By specifying the range in which you want to check whether or not the occurrence of a condition has occurred, only the specified range will be checked to see if the condition to be verified has occurred during simulation execution, and any conditions that were not verified will be displayed after simulation execution. Therefore, it is possible to easily grasp the state that has not been verified by pressing the input button after the simulation is executed for a specific range in the function description.

Effects of the Invention As described above, the present invention provides a verification item registered function symbol library in which function symbols whose states to be verified are registered in advance as verification items, and a function symbol library in the verification item registered function symbol library are provided. a function description registration means that describes and registers the function of a logic circuit using the simulator, and a verification execution state that sets a verification execution state flag set for each state to ON when a registered state to be verified occurs during simulation execution. inspection means,
By providing a verification execution state storage means for storing the state of the verification execution state flag, and an unverified item display means for displaying verification items for which the verification execution state flag of the verification execution state storage means is off after the simulation ends, verification can be performed. By describing the function of the logic circuit using the function symbols in the item registered function symbol library, checking whether a state that should be verified has occurred during the simulation, and displaying the state that was not verified after the simulation is completed, After running the simulation, it is possible to easily understand the state that was not verified by the Shicho Nirejon Kabatan.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the functional verification method for a logic circuit in the first embodiment of the present invention, and FIG. 2 is a diagram showing how a function description using symbols in the verification item registered function symbol library is sent to the function description registration means. A block diagram showing an example of registration, Fig. 3 is an explanatory diagram showing an example of pre-registered verification items for an adder, which is a functional symbol, and Fig. 4 shows a verification of the adder in the verification execution state storage means. FIG. 5 is an explanatory diagram showing an example of the initial state of the execution state flag, FIG. 5 is an explanatory diagram showing an example of the state of the verification execution state flag for the adder of the verification execution state storage means during simulation execution, and FIG. 6 is the verification diagram. An explanatory diagram showing an example of the state of the verification execution state flag for the adder of the execution state storage means after simulation execution, and FIG. 7 is an explanatory diagram showing an example of display of unverified contents displayed on the unverified item display means , FIG. 8 is a block diagram of a method for verifying functions of a logic circuit according to the second embodiment of the present invention, and FIG. 9 is a diagram showing a function description registering means for describing functions using symbols in the function symbol library with verification items registered. FIG. 1O is a block diagram showing an example of specification of the verification execution state inspection range specification means for the function description registration means. 11... Verification item registered function symbol library, 12... Function description registration means, 13...
...Simulator, 14...Verification execution state inspection means, 15...Verification execution state storage means, 16
...Unverified item display means, 21... Verification item registered function symbol library, 22...
... Function description registration means, 23 ... Simulator, 24 ... Verification execution state inspection means, 25 ...
... Verification execution state storage means, 26 ... Unverified item display means, 27 ... Verification execution state inspection range designation means, 31.33 ... Flip-flop,
32...Adder, 34...Constant multiplier.

Claims (2)

[Claims] (1) In a functional verification method for a logic circuit equipped with a simulator, a verification item registered functional symbol library in which functional symbols whose states to be verified are registered in advance as verification items is registered, and the verification item registered functional symbol library a function description registration means for describing and registering a function of a logic circuit using a function symbol inside; and a verification execution state flag set for each state when the registered state to be verified occurs during simulation execution; a verification execution state checking means for setting the verification execution state flag to ON; a verification execution state storage means for storing the state of the verification execution state flag; and an unverified checker for displaying verification items for which the verification execution state flag of the verification execution state storage means is OFF. item display means, describes the function of the logic circuit using the function symbol in the verification item registered function symbol library and registers it in the function description registration means, and displays the function of the logic circuit in the verification execution state storage means. The verification execution state flag for the verification item of the functional symbol used in the description is set to an off state and stored, the function description of the function description registration means is input to the simulator to execute the simulation, and the verification execution state check is performed. The means compares the state of the functional symbol at the time of simulation execution with the state to be verified for the functional symbol, and if a state to be verified occurs, turns on the verification execution state flag and executes verification in the verification execution state storage means. A state of a status flag is stored, and the verification execution status flag stored in the verification execution status storage means is checked in the unverified item display means to display verification items whose verification execution status flag is OFF. Functional verification method for logic circuits. (2) In a functional verification method for a logic circuit equipped with a simulator, a verification item registered functional symbol library in which functional symbols whose states to be verified are registered in advance as verification items is registered, and the verification item registered functional symbol library a function description registration means for describing and registering the function of a logic circuit using function symbols in the function description; and a verification execution state check for specifying whether or not to check the verification execution state for any function symbol in the function description. a range specifying means; a verification execution state checking means for setting on a verification execution state flag set for each state when the registered state to be verified occurs during simulation execution; A verification execution state storage means for storing a state, and an unverified item display means for displaying a verification item for which a verification execution state flag of the verification execution state storage means is OFF, Functions of a logic circuit are described using function symbols and registered in the function description registration means, and among the function symbols registered in the function description registration means, a function symbol whose verification execution state is to be checked is checked for the verification execution state. The verification execution state flag for the verification item of the function symbol specified by the range specification means and specified by the verification execution state inspection range specification means in the verification execution state storage means is set to an off state and stored, and the function description registration is performed. A description of the function of the means is input to a simulator and a simulation is executed, and the verification execution state checking means determines the state of the functional symbol specified by the verification execution state inspection range specifying means at the time of simulation execution and what should be verified for the functional symbol. If a state to be verified occurs, the verification execution state flag is turned on, the verification execution state storage means stores the state of the verification execution state flag, and the unverified item display means displays the verification execution state. 1. A method for functionally verifying a logic circuit, comprising: inspecting a verification execution state flag stored in a storage means; and displaying verification items for which the verification execution state flag is off.