JPS63123136A - Logical simulator - Google Patents

Abstract

PURPOSE:To attain the comprehensive judgement of simulation and to attain the efficient simulation by providing a memory to hold the change number of a status value in making a pair with the memory to hold the status value. CONSTITUTION:It is necessary to re-write and update the status value of the circuit, which is changed during the logical simulation execution, at the corresponding address area of a status value storing memory 1. Then, an address (a) to be changed and a status value (b), which is changed, are sent, the status value storing memory 1 writes status value data (b) into the address (a). Simultaneously, the contents of a status value change number storing memory 2 are read and outputted as a reading change number (c) by the address (a). For the change number (c), '1' is added in an adder 3, goes to a new change number (d), the new change number (d) are re-written into the area of the said address (a) of the state value change number storing memory 2 and the change number is updated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic simulator, and more particularly to a hardware logic simulator.

PRIOR ART Details of such conventional logic simulators are disclosed in the following documents. In other words, the 21st National Conference Proceedings of the Information Processing Society of Japan (7E-1 to 7
E-4), Information Processing Society of Japan October 1984 issue 9.1048-p, 1055, also published by the Information Processing Society of Japan, and Information Processing Box 26th National Conference Proceedings (7P-4 to 7P-), also published by the Information Processing Society of Japan. 6) and other documents.

In such conventional logic simulators, there is no means for checking how well the simulation model to be simulated operates, making it difficult to check the comprehensiveness of the simulation. As a result, circuits that cannot be completely simulated (test cases) are manufactured, and bugs may be discovered later, or simulations using redundant test cases may be performed, resulting in a large amount of man-hours. It has the disadvantage of being expensive.

The present invention has been made to solve the above-mentioned drawbacks of the conventional ones, and its purpose is to make it possible to grasp the number of changes in the state value of the circuit to be simulated. An object of the present invention is to provide a logic simulator that enables efficient simulation by making it possible to judge the comprehensiveness of simulation.

1. According to the present invention, there is provided a logic simulator having a state value storage memory for storing state values of a circuit to be simulated in respective assigned addresses, the logic simulator having state value storage memories corresponding to each address of the state value storage memory, respectively. an address area of the state value storage memory corresponding to the state value each time the state value changes; A logic simulator characterized in that the state value after the change is written in the state value, and the number of changes stored in the address area of the state value change number storage memory corresponding to the changed state value is updated. can get.

11 pieces The present invention will be described in detail below using the drawings.

The figure is a block diagram of an embodiment of the invention. In the figure,
The state value storage memory 1 is for storing all the circuit state values of the circuit to be simulated, and addresses are assigned to each state value to be stored. There is a state value change number storage memory 2 provided as a pair with this memory 1, and is used to store the number of times each state value has changed in an address area allocated corresponding to each state value. .

A certain state value changes and this state value is stored in state value storage memory 1.
When writing to the corresponding address, the contents of the corresponding address of the state value change number storage memory 2 are simultaneously read out and supplied to one of the adders 3.

"1" is always applied to the external power of this adder 3, and "1" addition processing is performed. This addition output is rewritten to the corresponding address area in the state value change number storage memory 2 to update the contents.

In such a configuration, it is necessary to rewrite and update the changed state value of the circuit in the corresponding address area of the state value storage memory 1 during execution of the logic simulation. Therefore, since the address a to be changed and the changed state value S are sent, the state value storage memory 1 writes the state value data b to the address a. At the same time, the contents of the state value change number storage memory 2 are read out using this address a, and the number of changes C is read out.
Output as . This number of changes C is "1" in the adder 3.
'' is added to obtain a new number of changes d, and this new number of changes d is rewritten in the area of the address a of the state value change number storage memory 2, thereby updating the number of changes.

In this way, the state value change number storage memory 2 always holds the state value change numbers of all circuits in the simulation target circuit as the latest information.

Therefore, by reading out the contents C of the state value change number storage memory 2 after the simulation is completed, it is possible to grasp the execution state of the simulation. That is, by using the contents C of this memory 2, it is possible to identify and recognize a circuit for which the number of changes in the circuit state value is insufficient among all the circuits to be simulated, and it is possible to perform a simulation targeting this circuit again. Become.

Further, test cases targeting sufficient circuits can be omitted, and therefore efficient simulation can be realized.

As described in detail, according to the present invention, by providing a memory that stores the state value and a memory that stores the number of changes in the state value, it is possible to judge the comprehensiveness of the simulation, resulting in efficient simulation. This has the effect of making it possible to implement the following.

[Brief explanation of the drawing]

The figure is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 1... State value storage memory 2... State value change number storage memory 3...
adder

Claims (1)

[Claims] A logic simulator having a state value storage memory for storing a state value of a circuit to be simulated at each assigned address, the logic simulator having an address corresponding to each address of the state value storage memory, and having a state value storage memory that stores a state value of a circuit to be simulated at each assigned address. It includes a state value change number storage memory for storing the number of changes in the state value, and each time the state value changes, the state value after this change is written to the address area of the state value storage memory corresponding to this state value, and . A logic simulator characterized in that the number of changes stored in the address area of the state value change number storage memory corresponding to the changed state value is updated.