JP2003345855A - Coverage measuring method and apparatus therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a coverage measuring method and an apparatus therefor which can measure a coverage regarding a combination of a plurality of test inputs given in time series. <P>SOLUTION: A definition table 20 in which the plurality of test inputs given in time series are defined and an event detecting operation description 22 including a coverage matrix table 22 are generated. The coverage matrix table 22 consists of a plurality of array elements corresponding to the combination of the plurality of test inputs. The event detecting operation description 22 after initializing the coverage matrix table 22 detects the combination of the test inputs, increases array elements corresponding to the detected combination, and counts its detection frequency. Then a coverage is calculated according to the updated coverage matrix table 22. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for measuring coverage, and more particularly, to a simulation of a logic circuit described in a predetermined language in response to a plurality of test inputs given in time series. The present invention relates to a method and an apparatus for measuring a coverage using a logic simulator to be executed.

[0002]

2. Description of the Related Art With the generalization of logic circuit design using HDL (Hardware Description Language), various code coverage tools are being used by EDA (Electronic Design Automation).
n) Provided by the vendor. Among them, VHDL and
The code coverage tool for a logic circuit described in Verilog-HDL executes a simulation by inputting a test pattern, and whether each statement in HDL is activated (code coverage) and whether all branches in HDL are covered. (Pasca coverage) and evaluate. These are all for evaluating how a current DUT (Design Under Test) operates according to an input test pattern.

FIG. 7 shows an example of an HDL description. In this example, there are five statements ST1 to ST5. Here, assuming that X = 1, the path P among the paths P1 and P2
1 is activated, the pass coverage is 50% (= 1
/ 2). Also, since three statements ST1 to ST3 of the five statements are activated,
Code coverage is 60% (=＝).

A method similar to the above is disclosed in Japanese Patent Laid-Open No.
No. 83 is disclosed. This method verifies how frequently an event (for example, a state machine) of a predetermined logic circuit has occurred.

In addition, a recent ED called a verification tool
Among the A tools, there is a coverage tool that can verify whether a combination of states of a plurality of state machines is covered. Hereinafter, an example thereof will be described with reference to FIGS.

FIG. 8 shows a state transition diagram of the state machine 1, and FIG. 9 shows a state transition diagram of the state machine 2. FIG.
As shown in the figure, the state machine 1 has four “0” to “3”.
It has two states. As shown in FIG. 9, the state machine 2 has five states “0” to “4”. In the figure, arrows indicate the direction of state transition.

FIG. 10 shows the result of verification by the verification tool. For example, when the state of the state machine 1 becomes “0” and the state of the state machine 2 becomes “0”, it occurs three times, and the state of the state machine 1 becomes “0” and the state of the state machine 2 becomes “0”. When it becomes "1", it has happened five times, but when the state of the state machine 1 becomes "0" and the state of the state machine 2 becomes "2", it has never occurred.

[0008]

When the conventional coverage tool as described above is used, it is possible to detect a fault in a logic circuit, but it is impossible to detect all faults. All of the conventional coverage tools execute simulations in response to test inputs at a certain time, and only detect defects that occur at that time.
This is because time series combinations of test inputs are not considered. One of the problems caused by a combination of a plurality of inputs that differ in time is a data hazard in a pipeline operation of a microcontroller. Hereinafter, an example thereof will be described with reference to FIGS.

The pipeline operation shown in FIGS. 11 and 12 includes four stages of decoding, reading, executing, and writing. Therefore, each instruction is processed in these four stages.

The instruction "ADD R1, R2" means that the value of the register R2 is added to the value of the register R1, and the result is stored in the register R1. The instruction "SUB R
"1, R2" means that the value of the register R2 is subtracted from the value of the register R1, and the result is stored in the register R1. The instruction "NOP" means that nothing is processed.

FIG. 11 shows a case where a data hazard occurs, and FIG. 12 shows a case where a data hazard does not occur.

In the case of FIG. 11, the instruction "ADD R1, R
2 ", the instruction" SUB R1, R2 ", the instruction" NOP ",
Processing is performed in the order of the instruction “NOP”. In this case, the cycle T
At +1, reading is performed in the register R1 in order to process the instruction “SUB R1, R2”. Thereafter, in cycle T + 2, writing is performed in the register R1 in order to process the instruction “ADD R1, R2”. That is, although the addition result must be read from the register R1 after the addition result is written into the register R1, the addition result is written in the register R1 after the reading for the subtraction is performed. Has been done. Such a defect is a data hazard in the pipeline operation.

On the other hand, in the case of FIG.
1, R2 ", the command" NOP ", the command" NOP ", and the command" SUB R1, R2 ". In this case, in cycle T + 2, writing is performed in the register R1 in order to process the instruction “ADD R1, R2”. afterwards,
In cycle T + 3, reading is performed in the register R1 in order to process the instruction “SUB R1, R2”. That is, after the addition result is written to the register R1, the addition result is read from the register R1. Therefore, the above-mentioned data hazard does not occur.

FIG. 11 shows a conventional code coverage tool.
In either case or FIG. 12, only the same verification result can be obtained, so that the data hazard generated in the case of FIG. 11 cannot be detected.

A main object of the present invention is to provide a method and an apparatus for measuring coverage in consideration of a time-series combination of test inputs.

A specific object of the present invention is to provide a coverage measurement which can measure not only how a logic circuit operates but also how a test input is given in time series. A method and apparatus are provided.

[0017]

SUMMARY OF THE INVENTION A coverage measuring method according to the present invention uses a logic simulator for executing a simulation of a logic circuit described in a predetermined language in response to a plurality of test inputs given in time series. A coverage measuring method, comprising a detecting step and a counting step. The detecting step detects a combination of test inputs. The counting step counts the number of times the combination of the detected test inputs is detected.

A coverage measuring apparatus according to the present invention is a coverage measuring apparatus using a logic simulator for executing a simulation of a logic circuit described in a predetermined language in response to a plurality of test inputs given in time series. And detecting means and counting means. The detecting means detects a combination of test inputs. The counting means counts the number of times the combination of test inputs detected by the detecting means is detected.

A coverage measurement program according to the present invention causes a computer to execute the above steps, and a computer readable storage medium according to the present invention stores the coverage measurement program.

According to the present invention, a combination of a plurality of test inputs given in time series is detected and the number of times of detection is counted, so that the coverage of the time series combination of test inputs is measured. As a result, a defect (a data hazard or the like in a pipeline) that cannot be detected by the conventional coverage tool can be detected.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding parts have the same reference characters allotted, and description thereof will be referred to.

FIG. 1 is a block diagram showing an overall configuration of a coverage measuring system according to an embodiment of the present invention.
With reference to FIG. 1, a coverage measurement system 10 performs a simulation of a DUT 12 described in RTL (Register Transfer Level) in a test vector
4 and a logic simulator 18 for outputting waveform data 16 as a result.

The logic simulator 18 is composed of a program for verifying the operation of a logic circuit described in HDL, and this program is a computer (not shown).
Installed in DUT 12, test vector 14
And the waveform data 16 are stored in a storage device of the computer.

The coverage measurement system 10 further includes
Definition table 20 and coverage matrix table 2
2 is used. These are created by the user and stored in the storage device of the computer.

FIG. 2 shows an example of the definition table 20.
The definition table 20 defines a test input to be verified. In this case, particularly, the test input at a plurality of different times is defined. All test inputs may be defined, or some test inputs may be defined. The test input defined here is the test vector 14
Is given to the logic simulator 18.

In the example shown in FIG. 2, four test inputs in the current cycle T and the immediately preceding cycle T-1
And the four types of test inputs are defined and verified.

Here, the input pattern in the current cycle T is the same as the input pattern in the immediately preceding cycle T-1. “STORE R0” is an instruction to store a value in the register R0. “LOAD R0” is an instruction to read the value of the register R0. "ADD R0,
"R1" is an instruction for adding the value of the register R1 to the value of the register R0 and storing the result in the register R0.
“SUB R0, R1” is an instruction for subtracting the value of the register R1 from the value of the register R0 and storing the result in the register R0.

FIG. 3 shows an example of the initial coverage matrix table 22. The coverage matrix table 22 includes a plurality of array elements CT corresponding to combinations of test inputs at a plurality of times defined in the definition table 20.
_X_y (x = 0 to 3, y = 0 to 3). Each of array elements CT_x_y (x = 0 to 3, y = 0 to 3) indicates the frequency of occurrence of the corresponding test input combination.

In this example, since four test inputs in cycle T and four test inputs in cycle T-1 are to be verified, the coverage matrix table 22 has a 16 (= 4 × 4) array. Element CT_
x_y (x = 0 to 3, y = 0 to 3). Further, each of the array elements CT_x_y (x = 0 to 3, y = 0 to 3) is initialized to “0” by the event detection operation description 24.

FIG. 4 shows an example of the event detection operation description 24. The event detection operation description 24 includes an array element CT_x_y (x = 0) for the coverage matrix table 22.
, Y = 0 to 3), the definition of a test input (test vector), the initialization operation of the coverage matrix table 22, and the detection of a combination of test inputs (hereinafter, also simply referred to as “event”). The operation is described in Verilog-HDL. Hereinafter, the event detection operation description 24
Will be described more specifically.

In the routine (a), array elements CT_x_y (x = 0 to 3, y = 0 to 0) for the coverage matrix table 22 based on the definition table 20 shown in FIG.
The definition of 3) and the definitions of the test inputs OP and OP-1 are described. “Reg [7: 0]” is an array element CT_x
Each of _y (x = 0 to 3, y = 0 to 3) is defined as an 8-bit variable. “Reg [31: 0]” corresponds to cycle T
And the test input OP-1 in the cycle T-1 are defined as 32-bit variables.

In the routine (b), the array element CT_x_
y (x = 0 to 3, y = 0 to 3) are respectively set to “00 (16
Base number) "(=" 00000000 (binary number) "). Thereby, as shown in FIG.
The coverage matrix table 22 will be initialized.

In the routine (c), a combination (event) of the test inputs OP and OP-1 is detected, and an array element CT_x_y (x = 0 to 3, y) corresponding to the detected event is detected.
= 0 to 3) is described. Specifically, it describes that an event is detected and the number of occurrences of the event is counted. Thus, for example, test input OP in cycle T is “STORE” and test input OP-1 in cycle T-1
Is "STORE", the array element CT_0_0 corresponding to the event is incremented. Further, the test input OP in the cycle T is “ST
If it is "ORE" and the test input OP-1 in the cycle T-1 is "LOAD", the array element CT_1_0 corresponding to the event is incremented.

Next, the operation of the above-described coverage measuring device will be described.

First, the DUT 12 to be verified and the test vector 14 are given to the logic simulator 18. Here, the test input of the definition table 20 shown in FIG. Further, the event detection operation description 24 shown in FIG. As a result, the coverage measurement device operates as follows.

FIG. 5 is a flowchart showing a coverage measurement program for causing a computer to function as the coverage measurement device according to the present embodiment. Referring to FIG. 5, logic simulator 18 performs array element CT_x_y of coverage matrix table 22 in accordance with the given event detection operation description 24 routine (a).
(X = 0-3, y = 0-3) are defined (S1), and test inputs OP and OP-1 are further defined (S2).

Subsequently, the logic simulator 18 determines the array element CT of the coverage matrix table 22 in accordance with the given event detection operation description routine 24 (b).
_X_y (x = 0 to 3, y = 0 to 3) is initialized to “0” (S3). At this time, all array elements CT_x_y
Since (x = 0 to 3, y = 0 to 3) becomes “0”, the coverage becomes 0% (= 0/16).

Subsequently, the logic simulator 18 generates a DUT according to the given test vector 14 (test input).
The simulation of No. 12 is started (S4).

Subsequently, the logic simulator 18 detects the given combination (event) of the test input according to the routine (c) of the given event detection operation description 24 (S5). When a predetermined event is detected, an array element CT_x_y (x = 0 to 0) corresponding to the event is detected.
3, y = 0-3) is incremented. On the other hand, if no event is detected, the process skips step S7 and proceeds to step S8. During execution of the simulation, the above steps S5 to S7 are repeated (S8), whereby the coverage matrix table 22 is updated.

When the simulation is completed, the logic simulator 18 outputs the updated coverage matrix table 22 (S9). FIG. 6 shows an example of the updated coverage matrix table 22.

Then, coverage is calculated based on the updated coverage matrix table 22. In the example shown in FIG. 6, only the array element CT_3_3 remains “0” and the remaining array elements are all incremented, so that the coverage is 93.8% (= 15/16).

As described above, according to the embodiment of the present invention, a combination (event) of a test input in cycle T and a test input in cycle T-1 is detected, and array element CT_x_y (x = 0
Since (3, y = 0 to 3) is incremented, it is possible to measure the coverage of a time-series combination of test inputs. Therefore, a defect (a data hazard or the like in a pipeline) that cannot be detected by the conventional coverage tool can be detected.

The above embodiment can be used together with a conventional coverage tool. When used together, the degree of achievement of the function verification can be measured more accurately.

Further, in the random test using random inputs, it is possible to detect not a defect due to the influence of the input pattern at a certain time but a defect due to the interaction of the input patterns at a plurality of times. Conventionally, in the random test, there was no appropriate coverage measurement standard.However, the coverage measurement method according to the above-described embodiment is an important index for setting the verification target, confirming the progress, and determining the end time. Become.

Although the event detection operation is described in HDL in the above embodiment, it can be described in C language or the like. When written in C language, PLI (Peripheral Language Int.)
interface with C language, which is a standard function of logic simulators such as erface). PLI uses Verilog-HDL and C, which are used in many logic simulators.
It is an interface with languages and is also an IEEE standard.
Although not a standard, many logic simulators employ their own interface between VHDL and C language.

In the above embodiment, the input of the logic circuit is to be verified. However, since a logic simulator is used, the internal signal of the logic circuit can be verified. In a pipeline operation or the like, it is also possible to measure the time-series coverage of an instruction that is actually issued or executed. Further, the present invention is also applicable to logic circuits that are affected by external factors, such as communication and external bus operation.

The coverage measurement program in the above embodiment may be distributed through a computer network or the like.
It may be recorded on a computer-readable recording medium such as R, CD-RW, DVD, or flexible disk and distributed in some cases.

The embodiment of the present invention has been described above.
The above-described embodiment is merely an example for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit thereof.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a coverage measuring device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a definition table in FIG.

FIG. 3 is a diagram illustrating an example of an initialized coverage matrix table in FIG. 1;

FIG. 4 is a diagram illustrating an example of an event detection operation description including a coverage matrix table in FIG. 1;

5 is a flowchart showing a coverage measurement program for causing a computer to function as the coverage measurement device shown in FIG.

6 is a diagram illustrating an example of a coverage matrix table updated by the simulator in FIG. 1;

FIG. 7 shows an example of a conventional code coverage tool described in HDL.

FIG. 8 is a state transition diagram of a certain state machine to be verified by a conventional coverage tool.

9 is another state machine different from the state machine shown in FIG.
FIG. 6 is a state transition diagram of two state machines.

FIG. 10 is a diagram illustrating a result of detecting a combination of states of the two state machines illustrated in FIGS. 8 and 9 using a conventional coverage tool.

FIG. 11 is a flowchart showing a pipeline operation when a data hazard occurs.

FIG. 12 is a flowchart showing a pipeline operation when no data hazard occurs.

[Explanation of symbols]

10 Coverage measurement system 12 DUT 14 Test Vector 18 Logic simulator 20 Definition table 22 Coverage matrix table 24 Event detection operation description

Continuation of front page    (72) Inventor Kenji Kiyose             800 Miyake, Yasu, Yasu-cho, Yasu-gun, Shiga Prefecture             IBM Japan Ltd. Yasu Business             Inside F term (reference) 2G132 AA01 AB02 AC11 AE23 AL11                 5B046 AA08 BA09 JA05

Claims (8)

[Claims] 1. A coverage measuring method using a logic simulator for executing a simulation of a logic circuit described in a predetermined language in response to a plurality of test inputs given in time series, wherein: A coverage measuring method, comprising: a detecting step of detecting a combination; and a counting step of counting the number of detections of the detected combination of test inputs. 2. The coverage measurement method according to claim 1, further comprising: defining a matrix table including a plurality of array elements corresponding to the plurality of test input combinations; and defining the defined matrix table. An initializing step of initializing; and the counting step increments an array element corresponding to the detected combination of test inputs. 3. The coverage measurement method according to claim 2, further comprising: outputting an updated matrix table by incrementing the array elements; and performing the increment based on the output matrix table. A coverage calculating step of calculating a ratio of array elements. 4. A coverage measuring device using a logic simulator for executing a simulation of a logic circuit described in a predetermined language in accordance with a plurality of test inputs given in a time series, wherein: A coverage measuring device, comprising: a detecting means for detecting a combination; and a counting means for counting the number of times the combination of test inputs detected by the detecting means is detected. 5. The coverage measurement device according to claim 4, further comprising: a definition unit that defines a matrix table including a plurality of array elements corresponding to the combination of the plurality of test inputs. Initialization means for initializing a matrix table, wherein the counting means increments an array element corresponding to a combination of test inputs detected by the detection means. 6. The coverage measuring device according to claim 5, further comprising: an output unit that outputs a matrix table updated by incrementing the array element; and a matrix table that is output by the output unit. And a coverage calculating means for calculating a ratio of array elements incremented by the counting means. 7. A coverage measurement program for causing a computer to execute the steps according to claim 1. Description: 8. A computer-readable storage medium storing the coverage measurement program according to claim 7.