JPH0726765Y2 - Macro cell delay information retrieval display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a logic design support device for searching and displaying delay information of a macro cell when a logic diagram is input in logic design.

[Prior Art] In circuit design of LSIs (Large Scale Integrated Circuits), a technique of simulating, that is, constructing a model of a target circuit on a computer and simulating its operation (simulation) is It is used as a powerful tool for design verification. A logic simulation for a digital circuit is typical of this simulation technique.

In the logic simulation, the target circuit is grasped as a combination of structural units having a predetermined logic operation function called a macro cell, and the simulation is executed at the level of this macro cell. For example, a collection of logic gate elements,
ALUs (arithmetic and logic unit), counters, storage elements, etc. are handled as macro cells.

The logic simulation device that executes the logic simulation is accompanied by a logic diagram input device that constructs and inputs a logic diagram of a target circuit (a circuit diagram expressed with a macro cell as a structural unit). Various kinds of macro cells are prepared as a library in the logic diagram input device, and the operator selects each macro cell one by one and constructs the logic diagram by designating the mutual connection relationship. For example, a plurality of types of macrocells having different driving capabilities, input resistances, input capacitances, etc. are prepared in the library even if the logic gate devices have the same function (for example, the same NAND circuit device).

The logic diagram input device is equipped with an image display device such as a display, and the logic diagram under construction is always displayed. The operator adds macro cells one by one on the logic diagram displayed in the image and inputs the connection relationship with other macro cells to successively build the logic diagram.

The simulation model is input to the logic simulation device together with the completed logic diagram. The simulation model describes information about the logical operation function of various macro cells and information that is the basis for delay calculation of various macro cells, for example, information about the internal delay value, input capacity, output capacity, etc. of various macro cells.

The logic simulation device decodes the input logic diagram to grasp the types of macrocells forming the circuit and their connection states, and based on the information on the logic operation function supplied by the simulation model and the delay calculation. The logic simulation of the circuit is executed based on the information. Therefore, from the simulation result output by the logic simulation apparatus, it is possible to obtain not only knowledge about the logical operation of the circuit but also knowledge about the delay value in each macrocell.

The conventional typical method for finding the delay value of a macro cell is to use this logic simulation. The procedure of this method including the flow of logic simulation is shown in FIG. In the figure, after the logic diagram input (1), the simulation model (3) is used to execute the logic simulation (4), and the macrocell delay analysis (5) is analyzed based on the output simulation result (4). I was going.

Arrangement and wiring of macro cells are performed by the logic diagram input (1), and then the logic simulation (2) is executed using the netlist and the simulation model (3) created by the logic diagram input.

The delay value of the macro cell can be known by analyzing the delay of the macro cell (5) by looking at the simulation result (4) output as a result.

[Problems to be Solved by the Invention] As described above, since the conventional method uses the logic simulation, there is a problem that it takes time and labor to know the delay value of the macro cell. In particular, the delay value of each macrocell does not directly appear in the result of the logic simulation, and the procedure of analysis as described above is necessary, which also contributes to extra time and effort. .

Moreover, in the conventional method, the delay value of the specific macrocell desired to be obtained can be obtained only after performing the logic simulation of the target circuit. The delay value of a macro cell cannot be known in advance. Therefore, since the logic simulation is not performed on the logic diagram composed of macrocells that have been thoroughly examined for the delay value, it was necessary to repeatedly perform the logic simulation until the circuit was finally determined. . That is, there is a problem that the efficiency of circuit design is poor.

When selecting a macro cell in the logic diagram in the process of constructing the logic diagram before execution of the logic simulation, if the delay value of the macro cell is to be known in advance, the manual calculation is conventionally performed by referring to the manual. There was nothing else. That is, the delay value of a specific macro cell is known by referring to the manual for the specific macro cell for which the delay value is desired and the macro cells connected to its input side and output side, and performing manual calculation based on the calculation formula. There was nothing else. However, this method has a problem that it is inefficient.

Furthermore, in the method using this manual, the information that is the basis of delay calculation does not always match between the referenced manual and the simulation model. For this reason,
Even if macro cells are selected based on a delay value based on a manual to construct a logic diagram and a logic simulation is performed on this logic diagram, there is a problem that an expected result may not be obtained.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a macro cell delay information search and display device that efficiently obtains a macro cell delay value and enables efficient circuit design. And

[Means for Solving the Problem] A delay information search and display device for a macro cell according to a first invention is connected to a logic diagram input device for constructing a logic diagram for displaying a connection state of a macro cell and inputting the logic diagram to a logic simulation device. A delay information search and display device for a macro cell used as a device, wherein a specific macro cell designated by an operator in the logic diagram during construction or after completion of construction in the logic diagram input device and an input side and an output side of the particular macro cell A delay value in the specific macro cell based on the type of macro cell connected to the logic simulation device and information that is a basis for delay calculation for each macro cell type included in the simulation model input to the logic simulation device. However, the delay value is added to the logic diagram displayed by the logic unit input device. The feature is that the image is displayed twice.

A delay information search and display device for a macro cell according to a second invention, which is used by being connected to a logic diagram input device for constructing a logic diagram for displaying a connection state of a macro cell and inputting the logic diagram to a logic simulation device. A device, a specific macrocell type specified by an operator, an environmental condition of the specific macrocell set by the operator, and a delay for each macrocell type included in a simulation model input to the logic simulation device. It is characterized in that the delay value in the specific macro cell is calculated and output based on the information on which the calculation is based.

[Operation] The retrieval display device of the delay information of the macrocell according to the present invention displays the delay value of the macrocell on the logic diagram by selecting the macrocell whose delay value is to be checked at the time of inputting the logic diagram. , The delay information of the macro cell is interactively output by setting the macro cell name and the environmental condition regardless of the logic diagram input.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an input / output flow chart of a delay information retrieval / display device for a macro cell according to the present invention. The macro cell delay information retrieval display device 8 inputs a logic diagram (1), selects a macro cell (7), performs delay calculation based on the simulation model (3), and outputs a delay value (9).
Can be displayed on the logical diagram.

That is, in the simulation model, as is well known, in addition to the logical operation function for each macro cell type, information that is a basis for delay calculation for each macro cell type is described. In addition, the operator inputs a logic diagram during or after the construction from the logic diagram input device. The delay information retrieval display device is based on the type of macro cell selected by the operator in the input logic diagram and its input side, and the macro cell connected to the output side, and the delay calculation described by the simulation model for them. The delay value is calculated based on the following information.

Although a calculation formula is required for the calculation, any one of many well-known calculation formulas may be used. The calculated delay value is displayed as an image by superimposing it on the logical diagram displayed by the display device included in the logical diagram input device (see FIG. 1).

Therefore, the delay value is calculated only for the desired macro cell without executing the logical simulation.
A desired delay value can be efficiently obtained. Further, during the process of constructing a logic diagram by the operator using the logic diagram input device, it is possible to know whether or not the delay value of the macro cell newly added on the logic diagram is appropriate before executing the logic simulation. .

Therefore, since the logic diagram input to the logic simulation device is composed of macro cells having an appropriate delay value, it is possible to reduce the number of times the logic simulation is repeatedly executed in order to determine the circuit configuration. That is, the circuit is designed efficiently. Also, since the delay value is displayed in a superimposed manner on the logical diagram displayed by the logical diagram input device,
It is easy to understand the delay value.

Furthermore, even if there is no logic diagram, fanout number, temperature,
By setting environmental conditions such as voltage (6), the delay information of the macro cell can be output (10).

That is, the delay information retrieval and display device is configured such that the desired macro cell type specified by the operator from the library of the logic diagram input device, the environmental condition of the macro cell set by the operator, and the macro cell type described by the simulation model It is also possible to calculate and output the delay value of the desired macro cell based on the information that is the basis of the delay calculation of.

Therefore, also in this case, since the delay value is calculated only for the desired macro cell without executing the logic simulation, the desired delay value can be efficiently obtained. Further, the operator can know the delay value of a macro cell to be newly added on the logic diagram before adding it on the logic diagram in the process of constructing the logic diagram using the logic diagram input device.

Therefore, the logic diagram input to the logic simulation device is composed of macrocells having an appropriate delay value, so that the number of times that the logic simulation is repeatedly executed to confirm the circuit configuration can be reduced, and the circuit design The efficiency of can be improved.

By selecting (picking) the macro cells to be placed when inputting the logic diagram, the rise delay value and fall delay value can be set in consideration of external environment conditions such as fan-out capacity (fan-in capacity), temperature, and voltage. Can be calculated and displayed.

Since the library defining the delay of the macro cell used at this time uses the same library as the simulation model (3), it matches the delay value of the macro cell obtained from the simulation result.

The macro cell delay information search / display system can also output a manual in which the macro cell delay information is described.

[Advantage of Device] As described above, according to the present invention, when examining the delay information of the macrocell in the logic design, the method of referring to the delay information of the macrocell becomes extremely easy, and the efficiency of the design work can be improved. Have.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an input / output flow chart of a delay information search / display device for a macro cell which is an embodiment of the present invention, and FIG. 2 is a conventional flow chart for searching delay information of a macro cell. In the figure, (1) is environmental condition setting, (2) is a logical simulation, (3) is a simulation model,
(4) is a simulation result, (5) is analysis of macro cell delay, (6) is environmental condition setting, (7) is macro cell selection, (8) is macro cell delay information retrieval display, (9) is delay value, (10) ) Indicates the delay information output of the macro cell, and (11) indicates the manual of the macro cell. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Scope of utility model registration request] 1. A delay information retrieval and display device for a macro cell used in combination with a logic diagram input device for constructing a logic diagram for displaying a connection state of a macro cell and inputting the logic diagram to a logic simulation device, said logic diagram input device. In the logic diagram during construction or after completion of construction, the type of macro cell connected to the input side and output side of the specific macro cell designated by the operator in the logic diagram, and the simulation input to the logic simulation apparatus. The delay value in the specific macro cell is calculated based on the information that is the basis of the delay calculation for each type of macro cell included in the model, and the delay value is displayed in the logical diagram displayed by the logical diagram input device as an image. A delay information search and display device for a macro cell, which is characterized by displaying images in an overlapping manner. 2. A delay information retrieval display device for a macro cell used in combination with a logic diagram input device for constructing a logic diagram for displaying a connection state of a macro cell and inputting the logic diagram to a logic simulation device, which is instructed by an operator. Based on the type of the specific macro cell, the environmental condition of the specific macro cell set by the operator, and the information that is the basis of delay calculation for each type of each macro cell included in the simulation model input to the logic simulation apparatus. A delay information search and display device for a macro cell, wherein a delay value in the specific macro cell is calculated and output.