JPS6116652U - Memory data display tester - Google Patents

Memory data display tester

Info

Publication number
JPS6116652U
JPS6116652U JP10151384U JP10151384U JPS6116652U JP S6116652 U JPS6116652 U JP S6116652U JP 10151384 U JP10151384 U JP 10151384U JP 10151384 U JP10151384 U JP 10151384U JP S6116652 U JPS6116652 U JP S6116652U
Authority
JP
Japan
Prior art keywords
data display
memory data
display tester
memory
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10151384U
Other languages
Japanese (ja)
Inventor
修二 佐藤
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP10151384U priority Critical patent/JPS6116652U/en
Publication of JPS6116652U publication Critical patent/JPS6116652U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例の構成説明図、第２図、第３図
は第１′図の実施例の要部の具体回路例であり、図中、
１は端末装置、２は中央処理装置、４はバス、５はメモ
リ、１０はメモリデータ表示試験器、１１はパリティエ
ラー信号発生部、１２はアドレスラッチ、１３はデータ
ラッチ、１４はアドレス表示、１５はデータ表示、２１
，２１２はパリテイチェック回路を示す。FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention, and FIGS. 2 and 3 are specific circuit examples of the main parts of the embodiment of FIG. 1'.
1 is a terminal device, 2 is a central processing unit, 4 is a bus, 5 is a memory, 10 is a memory data display tester, 11 is a parity error signal generator, 12 is an address latch, 13 is a data latch, 14 is an address display, 15 is data display, 21
, 212 indicates a parity check circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メモリを接続したバス上に出力されるリード、ライトデ
ータのエラーを検知する手段を具える端末装置に接続さ
れ、リードまたはライトのパリテイエラー信号を発生す
る手段と、該パリテイエラー信号に対応する前記端末装
置のバス上のアドレス、データをラツチ子る回路と、該
ラッチ回路の出力により充電表示する表示部とを具えた
ことを特徴吉するメモリデータ表示試験器。Means for generating a read or write parity error signal, connected to a terminal device having means for detecting errors in read or write data output on a bus connected to the memory, and corresponding to the parity error signal. A memory data display tester comprising: a circuit that latches addresses and data on a bus of the terminal device; and a display section that displays charging based on the output of the latch circuit.
JP10151384U 1984-07-05 1984-07-05 Memory data display tester Pending JPS6116652U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10151384U JPS6116652U (en) 1984-07-05 1984-07-05 Memory data display tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10151384U JPS6116652U (en) 1984-07-05 1984-07-05 Memory data display tester

Publications (1)

Publication Number Publication Date
JPS6116652U true JPS6116652U (en) 1986-01-30

Family

ID=30660944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10151384U Pending JPS6116652U (en) 1984-07-05 1984-07-05 Memory data display tester

Country Status (1)

Country Link
JP (1) JPS6116652U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63119203U (en) * 1987-01-29 1988-08-02
JPH0483318A (en) * 1990-07-25 1992-03-17 Ckd Corp Manufacture of solenoid

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63119203U (en) * 1987-01-29 1988-08-02
JPH0451443Y2 (en) * 1987-01-29 1992-12-03
JPH0483318A (en) * 1990-07-25 1992-03-17 Ckd Corp Manufacture of solenoid
JP2568300B2 (en) * 1990-07-25 1996-12-25 シーケーディ株式会社 Solenoid manufacturing method

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