JPS63163934A - Bus trace system - Google Patents

Abstract

PURPOSE:To facilitate fault tracing and performance evaluation by recording data generated on plural buses with the value of a timer counter. CONSTITUTION:Exclusive trace memories 20a-20c are provided in the buses 100a-100c. The clock of a clock generation means 24 is counted in the timer counter 22 and the value of the timer counter 22 is recorded in the trace memories 20a-20c with bus data through a recording means 25. Since the respectively common timer counter 22 records generation time in data on plural buses, time relation between the buses is made clear and fault analysis and performance evaluation is facilitated.

Description

[Detailed Description of the Invention] [Summary] A bus tracing method that records data generated on multiple buses together with count data of a timer counter.
The time of occurrence is recorded to clarify the time relationship between buses.

[Industrial application field]

The present invention relates to improvements in bus tracing methods.

Bus tracing, which records data occurring on a bus in the order in which it occurs, is well known for purposes such as analyzing failures.

However, in recent years, multiprocessor systems with multiple buses have become a problem, and when dedicated trace memory is allocated to these multiple buses and traced independently, the time relationship between the buses is unclear. There is.

Therefore, there is a need for a bus tracing method that solves the above problems.

[Conventional technology]

FIG. 3 (al is an explanatory diagram of a bus trace in one set of buses, and FIG. 3(b) is an explanatory diagram of a bus trace in a multiprocessor system.

FIG. 3 fa)-(1) is a diagram showing an example of bus connection,
Processor unit CPUI, memory 2. An adapter 3 and a bus tracer 4 are each connected to a bus 100.

The path tracer 4 sequentially records data flowing on the bus 100 in the order of occurrence in the trace memory 5 for a certain period of time from the running point of a designated program. bus 100 at the timing when the strobe signal is detected. i.e. address bus.

All data generated on the data bus and control bus are written to the trace memory 5.

FIGS. 3(a)-(■) are diagrams showing the data in the trace, and show how the data is stored in the trace memory 5 in the order of occurrence (bus data 0.1, . . . ).

Figure 3 (bl-(1) shows a multiprocessor connection example (
(with cache) includes an internal bus 100a that transfers data between the processor 9 and the cache memory 10, a local bus 100b that allows each processor unit CPU0 and CPUI to access individual memories 11, 14, etc., and CPU0. It is composed of multiple buses such as a common bus 1oOc through which the CPUI accesses the common memory 13, and the CPU0. The CPUIs access the bus asynchronously with each other.

As a method for tracing these plurality of buses, there is a first method (not shown in the figure) in which a dedicated trace memory 5a to 5C is provided for each bus and traced independently [Fig. 3(b)-(I)]. A second method may be to latch the data on the bus into registers, scan and read the registers, and record them in a set of trace memories.

However, in the first method, data within the same bus is recorded in the respective trace memories 5a to 5C in the order of occurrence, but it is not possible to identify the time relationship between the buses.
(1-(II)) In the second method, data generated simultaneously between buses is recorded in the scan order of the registers, so it is not possible to precisely know the time relationship between the buses.

[Figure 3 (bl-(n)) [Problems to be Solved by the Invention] As explained above, the conventional bus trace method for tracing multiple buses in a multiprocessor system The problem is that it is unclear.

On the other hand, there is also a desire to check the number of data generated within a predetermined time for performance evaluation, and an object of the present invention is to provide a bus tracing method that solves these problems.

[Means for solving problems]

For the above purpose, the bus tracing method of the present invention provides a dedicated trace memory (20a, 20bp20C) for each bus and a clock having a specified time width, as shown in FIG. (53); and a timer counter (22) that counts the clock (53).
and the count data (54) output from the timer counter (22) together with the data are stored in the trace memories (20a, 20).
b, 20c) and recording means (21) for recording are provided.

[Effect]

A timer counter 22 that counts a clock 53 having a predetermined time width is provided, and when data flows on the bus, the count data 54 of the timer counter 22 is stored together with the data in the corresponding trace memory (20a, 20b, 20
c).

The predetermined time width is from the CPU clock (μS) to several mS, etc., and the clock 53 is set based on the time relationship necessary for tracking.
Enter and set the time width data.

As described above, since the time of occurrence of data on multiple buses is recorded by the common timer counter 22,
The time relationship between buses becomes clear, making failure analysis and performance evaluation easier.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

FIG. 2(a) is an operation time chart, FIG. 2 (bl is a multi-tracer block diagram of the embodiment, and FIG. 2 (C1 is a diagram representing data in the trace memory of the embodiment).

The multi-tracer of the embodiment has an internal bus 100a.

This is an example applied to a multiprocessor system having a local bus 100b and a common bus 1, and bus tracers 4 with the same configuration perform bus tracing for each bus.
a, 4b, 4c, a time width setting counter 21, a timer counter 22, and a time width setting register 23.

Note that the clock generating means 24 shown in FIG. 1 corresponds to the time width setting counter 21 and the time width setting register 23, and the recording means 25 corresponds to the trace memories 20a to 20c and the trace control section 16a.

In the path tracer 4a shown in FIG. 2(b), 16a is a trace control unit, which identifies trace start address data, trace data length, etc. written in a plurality of registers 17a by a processor (not shown), starts tracing, A function to control the end, a function to set the start address of the trace memory 20a in the address counter 19a and perform step control for each write, and a function to detect the data strobe signal 51a on the internal bus 100a and send a write signal to the trace memory 20a. 52a to control writing.

Reference numeral 20a denotes a trace memory, which includes an internal bus 100a, a data line connected to the output line of the timer counter 22, and a storage area. established for each

In addition, 22 is a timer counter, and its output line (count data 54
(output line) of each trace memory 20a.

23 is a time width setting register connected to the data lines 20b and 20C, for example, the local bus 100.
21 is a time width counter that is connected to b and has time width data 56 set by the processor, which counts the CPU clock 53a based on the set time width data 56 and transfers the specified clock 53 to the timer counter 22. The output is as follows, and the same reference numerals represent the same objects throughout all other figures.

With the above configuration, the trace operation will be explained with reference to FIG. 2 (al operation time chart).

(11) Run the program by manually entering the trace start address, trace data length, time width data 56, etc. for each bus.

As a result, the timer counter 22 is reset and then starts counting by the clock 53.

(2) When the trace start data and the data output to the internal bus 100a match, the trace control unit 16a
outputs the write signal 52a at a predetermined timing after detecting the data strobe signal 51a, and outputs the write signal 52a to the internal bus 100a.
The count data 54 of the timer counter 22 is stored together with the upper bus data 50a at the address specified by the address counter 19a.

(3) Next, the bus data 5ob is placed on the local bus 100b.
flows, the trace control unit 19 of the path tracer 4b
b outputs the write signal 52b in the same manner as described above, and records the count data 54 of the timer counter 22 in the trace memory 20b together with the bus data 50b.

FIG. 2 (C1 represents the data in the trace memory, and represents that the count data 54 is recorded in correspondence with the data on the bus.

Therefore, by tracing the contents of each trace memory 20a, 20b, 20c based on the recorded count data 54, the time relationship between the buses becomes clear.

As described above, when the time width of the clock 53 is increased to about several milliseconds, a collection of data of the same count data 54 is recorded, and performance evaluation such as running time can be performed.

As described above, the time relationship of trace data on multiple buses is determined by the timer counter 2 that counts the predetermined clock 53.
It can be expressed by recording the count value of 2.

〔Effect of the invention〕

The present invention provides a bus trace method that records data generated on a plurality of buses together with the value of a timer counter that counts clocks having a predetermined time width, so that the time relationship between the buses becomes clear. Great effects can be obtained in troubleshooting, performance evaluation, etc.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 (al is an operation time chart, Fig. 2 (b) is a multi-tracer block diagram of the embodiment, and Fig. 2 (C) is data in the tracer memory. (1) is a diagram showing an example of bus connection, (I[) is a diagram showing data in the trace memory,
bl is an explanatory diagram of bus trace in a multiprocessor system, (1) is a diagram showing an example of multiprocessor connection (with cache), (II) is a diagram showing data in trace memory (Part 1)
, (I[I) is a diagram representing data in the trace memory (Part 2
), is. In the figure, 0.1 is the processor unit CPU. 2 is memory, 3 is adapter, 4.4at
4b, 4c are tracers, 5a, 5b, 5c are trace memories, 6 is a trace control unit, 9 is a processor, l
O is cache memory, 11.14 is individual memory, 12 is adapter, 13 is common memory, 16a,
16b and 16c are trace control units, 17a is a register,
18a is a control unit, 19a is an address counter, 20a, 20b, 20c are trace memories, 21 is a time width setting counter, 22 is a timer counter, 23 is a time width setting register, 24 is a clock generation means, 25 is a recording means, 53 is a clock, 53a is a CPU clock, 54 is counting data, 56 is time width data, 10
0.1ota, 100b, 100c are buses, 100a
is an internal bus, 100b is a local bus, and 100c is a common bus. C) (1) Diagram representing an example of bus connection (■) Diagram representing data in the trace memory Bus trace explanatory diagram for one set of buses Figure 3 (al (+) Representing an example of MaJ Reti processor connection (with cache) Diagram (■) Diagram showing data in trace memory (Part 1) (m
) Diagram representing data in trace memory (Part 2) Diagram explaining bus trace in a multiprocessor system (Part 3)

Claims (1)

[Claims] A bus trace in which data (50) generated on a plurality of buses (100a, 100b, 100c) are recorded in trace memories (20a, 20b, 20c) provided corresponding to the buses in the order of occurrence. A clock generation means (24) that generates a clock (53) having a specified time width, and a timer counter (22) that counts the clock (53).
and the count data (54) output from the timer counter (22) together with the data are stored in the trace memories (20a, 20).
b, 20c) is provided, and the data generated on the plurality of buses are recorded as the count data (54).
This is a bass tracing method that is characterized by recording data simultaneously.