JPH04180136A - Hardware tracer control circuit - Google Patents

Abstract

PURPOSE:To analize the internal working of a processor with high efficiency by instructing the start of a tracking operation after deciding that the address set when a processor contained in an information processor has an access to a memory included in the information processor is included in an address section of a comparison register. CONSTITUTION:The data comparators 4 and 5 compare the address set when an access is applied to a memory device with the address data on the comparison data registers 2 and 3. If the input address data is larger than the data on the register 2, a coincidence signal is sent to an AND circuit 6 through a data line 9. Meanwhile the coincidence signal is sent to the circuit 6 via a data line 10 if the input address data is smaller than the data on the register 3. Then the circuit 6 works when a control enable F/F 11 is set at 1 and the circuit 6 sends an operating signal to a tracer control part 7. Thus a control signal 100 is outputted to a tracer memory 8 and the start is instructed for the trace of a hardware state signal.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a control method for a hardware tracer.

[Conventional technology]

Conventionally, this type of hardware tracer writes the hardware status signal held in the hardware tracer every clock, and when the capacity is full, a write operation is performed to the area where it has already been written, and the previous status value is stored. By erasing it, the new state value was retained.

[Problems that the invention seeks to solve]

The above-mentioned conventional technology has a problem in that the hardware tracer has a finite capacity, so it does not always leave the necessary state values.

[Means to solve the problem]

The hardware tracer control circuit of the present invention has a register that holds the start point value of an address interval and a register that holds the end point value for comparison with an address when a processor in the information processing device accesses a memory device in the same device. a circuit that determines that an address when the processor accesses the memory device is included in the value of the address interval stored in the comparison register, and instructs the tracer memory to start tracing; and a tracer memory that records hardware status signals.

〔Example〕

Embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The hardware tracer control circuit of the present invention includes comparison data registers 2 and 3, a data comparison circuit 4.5, and an AND circuit 6.
, a tracer memory control circuit 7, a tracer memory 8, and a control enable F/Fil.

Comparison data registers 2 and 3 read and hold the value of an address interval for comparison with an address when a memory device in the information processing device accesses the memory device in the information processing device, and read and hold the value in the address interval by the maintenance diagnosis device in the device. The address to start tracing the wear status signal can be specified in the address range. Comparison data register 2 specifies the lower limit of the address range, and comparison data register 3 specifies the upper limit of the address range.

The data comparison circuits 4 and 5 compare and judge the address used when accessing the memory device with the address data held in the comparison data register 2.3.

The data comparison circuit 4 compares the values of the memory address data propagated via the data line 1 and the address data held in the comparison data register 2.

Similarly, the data comparison circuit S compares the values of the memory address data propagated via the data line 1 and the address data held in the data register 3.

The AND circuit 6 determines whether or not the memory address data propagated via the input signal line 1 is within the address interval specified by the data register 2. The control enable F/F receives the data on the signal line 10 which is the output of the data comparison circuit 5.
It is determined whether the comparator circuit is valid based on the signal of il.

That is, when the data comparison circuit 4 determines that the input address data is larger than the data in the register 2, a match signal is sent to the AND circuit 6 via the data line 9. Similarly, when the data comparison circuit 5 determines that the input address data is smaller than the data in the register 3, a match signal is sent to the AND circuit 6 via the data line 10.

When a coincidence signal is sent to both data lines 9 and 10 at the same time, and when control enable F/F 11 is “1”,
The data determination section 6 operates and sends an operation signal to the tracer memory control section 7.

When the AND circuit 6 determines that the memory address data transmitted through the input signal line 1 is within the address range specified by the comparison data registers 2 and 3, the tracer memory control circuit 7 controls the tracer memory 8. signal 10
Outputs 0 to instruct the start of tracing the hardware status signal.

For example, in the address range (1570-1585),
If a processor in an information processing device attempts to operate a tracer when an address is entered to access a memory device in the device, first write data to comparison data register 2 before starting data processing in the information processing device. [1570:
1, data (1585) are set in the comparison data register 3 from the maintenance/diagnosis device in the same device, and "1" is set in the control enable F/F 11.

When the information processing device is subsequently operated, the address for accessing the memory device is taken into the hardware tracer control circuit via the signal line 1.

When the processor in the information processing device accesses the memory device in the information processing device using address (1579),
Address data taken in via signal line 1 enters data comparison circuits 4 and 5. The data comparison circuit 4 receives the address data [:15] held in the comparison data register 2.
70) and is input via signal line 1 (1579)
Compare with.

As a result, since the address data input through signal line 1 is larger, a match signal is output to signal line 9. Similarly,
The data comparison circuit 5 compares the address data [1585] held in the comparison data register 3 with the address data (1579) input via the signal line 1. As a result, since the address data input through signal line 1 is smaller, a match signal is output to signal line 10. An address data match signal is output to signal lines 9-10. That is, [1570)≦
(1579)≦[1585] is established, and the AND circuit 6 is
A tracer memory operation signal 90 is sent to the tracer memory control circuit 7. The tracer memory control circuit 7 that receives the tracer operation signal causes the tracer memory 8 to start tracing the hardware status signal.

〔Effect of the invention〕

As described above, the hardware tracer control circuit according to the present invention can selectively collect necessary data, and therefore has the effect of facilitating efficient analysis of the internal operation of an information processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1... Input data line, 2... Comparison data register,
3... Comparison data register, 4... Data comparison circuit, 5... Data comparison circuit, 6... AND circuit, 7...
...Tray...Control enable F/F.

Claims (1)

[Claims] a register that holds a value of a starting point of an address interval for comparison with an address when a processor in the information processing device accesses a memory device in the information processing device;
A register that holds the end point value of the address interval, an access address for the memory device, and a hardware controller that determines whether or not the address is included in the address interval held in the register, and when the address is included in the corresponding address interval. A control circuit for instructing a wear tracer to start tracing, a tracer memory, and a means for starting tracing when an address for accessing a memory device is included in an address range held in the register. A hardware tracer control circuit comprising: