JPS59178553A - Debugging system - Google Patents

Abstract

PURPOSE:To stop a data processing device only by detecting that read out flag is a specified pattern by writing a specified pattern corresponding to address in a flag section provided in a memory. CONSTITUTION:When reading data, address AD and read request signal RRQ are sent from an originator of the request. Data are read out from a data section MD 11, set to a register RDR 91 and sent to the originator of request as read data RD through an AND circuit 111. At this time, data are read out from a flag section MF 12 and set to a flag register RFR 62. A detecting circuit 112 checks whether the value is a specified pattern or not. If it is a specified pattern, a stop signal S1 is made on. Then, stop condition EF 13 is set through an AND circuit 121. While EF 13 is on, clock signal of a clock generating circuit 16 is stopped by an NOT circuit 14 and an AND circuit 15, and the system stops.

Description

[Detailed Description of the Invention] (Al Technical Field of the Invention The present invention relates to a debugging method for a data processing device, and in particular, it is possible to stop the operation of the data processing device by reading data at an arbitrary address. Regarding debugging methods.

(b) Technical background As data processing devices have become larger and more highly integrated in recent years,
It is desired that the debugging method for Test 1 diagnosis in the event of a failure in a data processing device, especially the commonly used address stop function, be improved in consideration of the data storage function necessary for failure analysis.

(C1 Prior Art and Problems Conventionally, there is an address stop method as a method for stopping a data processing device by reading data from a storage device.The addresses at this time include an operand address and an instruction address. Even in this case, the data processing device is stopped when the execution of the instruction that caused the address stop is completed.

With this method, even if the read data has changed due to a hardware failure or a program error, it will stop after the data has been processed.
There was a problem in that it was not possible to determine what kind of data the data was.

One way to compensate for this drawback is to detect a match between the read data itself and immediately stop the data processing device. However, even with this method, if the data in the read data is large, such as 8 bytes, , 8 bytes of data registers and collation circuits are required to match the operand data, which increases hardware consumption, increases the number of logic stages in the collation circuits, and increases the logic delay due to the machine cycles of the 7i data processing equipment. The disadvantage is that it may be impossible to obtain a coincident output and stop the data processing device during this period.

(dl) Purpose of the Invention In view of the above-mentioned conventional drawbacks, an object of the present invention is to provide a method for stopping a data processing device between machine cycles of the data processing device and before read data is processed. It is something to do.

According to the present invention, the present invention provides a data processing system having a storage device and a data processing device or control device that accesses the storage device. an address register that can be set, a match detection circuit between the output of the address register and the access address to the storage device, a flag bit of one or more pins as write data in addition to the original data, and a match detection circuit for detecting the match. A circuit that can set the flag focus to a specific data pattern depending on how the circuit matches, and a circuit that detects that the flag bit part of the data read from the storage device is a specific data pattern; This is achieved by providing a function to stop the operation of the data processing device or control device.

if) Examples of the Invention The present invention will be explained in detail below with reference to the drawings. The figure shows one embodiment of the present invention.

Normally, when writing data to a storage device, write data (same), address (AD), and write request signal (Will) are used.
l) is sent from the data processing device (not shown) that is the source of the write request. The write data (-D) is set in the write data register (WDR) 21, the address (8D) is set in the address register (ΔDR) 3, and the write control circuit (WE) receives the write request signal (WRQ). GEN) 4 is the write pulse (W
E) is generated at a predetermined timing and written to the data section (MD) 11 of the storage device.

In this operation, the comparison address register (cAR)
51 (7) Valid indicator (CAV) 52 is off (=
0) T: If present, the flag setting signal (FS) that is the output of the AND circuit (A4) 6 is turned off, and thereby the flag data (FD) that is the output of the specific flag pattern generation circuit (Gl) 7 is an invalid pattern. (For example, all "0"
”) data, and this is the write flag register (W
FR) 22 and the aforementioned write pulse (I
QE) is written to the flag section (MP) 12 of the storage device.

In addition, in this operation, the comparison address (CAD) is transmitted from an external device by some means (for example, by means of a data key on the operation panel of the data processing device).

or a register setting command from a service processor (not shown)] is set in advance in the comparison address register (CAR) 51, and at that time, the valid indicator (CAV
) 52 is on (=1), the address (AD) sent with the write request signal (WRQ) is compared with the value of the comparison address register (CAR) 51 by the comparison circuit (CI) 8. , when they match, the flag setting signal (FS) which is the output of the AND circuit (A4) 6 turns on, and the specific flag pattern generating circuit (Gl) 7
The flag data (FD'), which is the output of MF)
Written in 12.

Further, when reading data from a normal storage device, an address (AD) and a read request signal (RRQ) are sent from the data processing device that is the source of the read request. The address (8D) is set in the address register (8DR) 3, and the data read from the data section (MD) 11 of the storage device is set in the read data register (RDI?) old, and the data read from the data section (MD) 11 of the storage device is set in the flag section of the storage device. The data read from the (MF) 12 is set in the read flag register (RF'R) 92.

A read control circuit (R5GEN) 10 which receives the read request signal (1?RQ) generates a read strobe signal (1?s) at a predetermined timing, and when this strobe signal (R5) is on, the read data is Register (RDR) The value of 91 is ANDed by the AND circuit (AI)
111 as read data (Il+)) to the requesting data processing device.

At this time, the value of the read flag register (RFP) 92 is checked by the specific pattern data detection circuit (C2) 112 to see if it is a specific pattern, and if it is an invalid data pattern, the specific pattern data detection circuit (C
2) The stop condition signal (Sl) which is the output of 112 is off, but when it is a specific pattern, the stop condition signal (sl) is turned on and the AND circuit (A2) 12
1 through the clock stop condition flip-flop (
FFI) 13 is struck.

This clock stop condition flip-flop (FF1)
Reference numeral 13 denotes a cent/reset type flip-flop which, once set by the cent signal, will not be reset unless a reset signal (RESET) is received.

This clock stop condition flip-flop (FFI)
) 13 is on, the clock generation circuit (G2) is
) is the output of the clock signal (cLK) to each part of the system.
) will no longer appear and the system will stop.

(gl Effects of the Invention As explained in detail above, according to the present invention, data processing is possible by writing a specific pattern in advance in correspondence with an address in a flag section provided in a storage device of a data processing system. When a device accesses the storage device,
By simply reading the flag corresponding to that address and detecting that it is the specific pattern, it is possible to immediately stop the data processing device and prevent the data in the accessed storage device from being processed. This has the effect of facilitating failure analysis of data processing equipment.

[Brief explanation of the drawing]

The figure shows one embodiment of the present invention. In the figure, 51--1 comparison address register (CAR) 52
-------One valid indicator (CAV) 8---One comparison circuit (C1) 7---Specific flag pattern generation circuit (G1)
21----1 write data register (Dl?)
22---Write flag register (WI'R) 11
---Data section (MD) 12=--Flag section (MF) 91--1 Read data register (RDR) 92-
---Read flag register (RFP) 4--
Write control circuit (E GEN) 3 --- Address register (8DR) 112 -- Specific pattern data detection circuit (C2) 10 --- Read control circuit (
R3GEN) 13-----Clock stop condition flip-flop (FFI) 16-----Clock/7-digit generation circuit (G2) E--
--------Write pulse FS---------Flag setting signal FD------------Flag data S L---------Stop condition signal R5---Read strobe signal be. -Divination: Musu 1

Claims (1)

[Claims] In a data processing system that includes a storage device and a data processing device or control device that accesses the storage device, the data processing device or control device is provided with an address register that can be set with an arbitrary value from an external device, and the output of the address register is and the access address to the storage device, one or more flag bits in addition to the original data as write data, and a coincidence output from the coincidence detection circuit to detect the flag bits in a specific data pattern. and a function to stop the operation of the data processing device or control device when it is detected that the flag bit part of the data read from the storage device is a specific data pattern. A debugging method that is characterized by: