JPH02105241A - Memory fault detection circuit - Google Patents

Abstract

PURPOSE:To detect the faults of plural memory blocks in one time of DMA transfer by attaching an adder circuit and an expected value judging circuit at every memory block in the judgement of data written on a memory. CONSTITUTION:Two adder circuits 7 and 8 add every one constant number on data read out from the memory blocks 3 and 4, and output the results of addition, and also, output control signals 60 and 61 for the expected value judging circuits 11 and 12. The circuits 11 and 12 compare the addition results of the circuits 7 and 8 with the values of addition expected value registers 9 and 10 according to the signals 60 and 61 from the circuits 7 and 8, and output signals when they are different. A defect judging circuit 17 generates and holds data representing in which memory block a fault occurs by receiving output from the two circuits 11 and 12. A data generation circuit 16 for fault detection outputs data for fault detection to be written on the memory block, and it is connected to a data bus 18 via buses 33 and 34 and a buffer 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory failure detection circuit used in information processing devices and the like, and particularly to a memory failure detection circuit that can check a large capacity memory in a short time.

[Conventional technology]

Conventionally, memory failure detection has been performed by writing data to memory and checking whether the data is the same as the written data when reading it, but all data writing, reading, and comparison are performed by the central processing unit. (hereinafter referred to as CPU).

[Problem to be solved by the invention]

However, if all processing is performed by the CPU as described above, there is a problem that the time required for failure detection increases as the memory capacity increases. In particular, the time allotted for memory failure detection at the start of operation of the information processing apparatus is short, and there are cases in which all the memory cannot be checked, which poses a problem in terms of the reliability of the information processing apparatus.

[Means to solve the problem]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a memory failure detection circuit that can check a large capacity memory in a short time.

In order to achieve the above object, the present invention uses direct memory access (DMA) to write and read fault detection data to and from the fault detection target memory, and also uses the result of adding data within an arbitrary fixed address range during comparison. The above objective is achieved by comparing the expected value of the addition result prepared in advance.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Here, a case is shown in which the memory for fault detection is divided into two blocks. In FIG. 1, the CPU 1 has a data bus 18. Setting of data necessary for the memory failure detection circuit of the present invention and the start of operation are controlled via an address bus 19 and a control bus 20.

The DMA control 2 controls reading and writing of data using DMA.

The first memory block 3 is directly connected to an address bus 19 as well as a bus 29. Buffer 64 and bus 3
0 to the data bus 18. Further, the bus 29 is connected to the addition circuit 7, and the bus 30 is connected to the expected addition value register 9. Second memory block 4
also has the same connection relationship as the first memory block 3.

When using the memory fault detection circuit according to the present invention, dividing the memory subject to fault detection into blocks of small capacity can shorten the time required for fault detection, but this increases the cost of the circuit. It is desirable to determine the number of divisions in consideration of the performance of the DMA controller 2.

The memory control circuit 14 includes a memory selection register 1
Write permission or read permission (read/write signals) 21 and 22 is given to the memory block selected by the data in 3.

Which memory block to select and the types of write and read permissions are set by the CPUI when writing and reading data to the memory.

The failure detection data generation circuit 16 is a circuit that outputs failure detection data to be written into the memory block, and is connected to the bus 33. It is connected to data bus 18 through buffer 15 and bus 34.

The two adder circuits 7 and 8 add one constant to the data read from the memory blocks 3 and 4, and output the results, as well as expected value determination circuits 11 and 12.
0 control signals 60 and 61 are output.

Two expected value determination circuits 11 and 12 combine the addition results of addition circuits 7 and 8 with the values of addition expected value registers 9 and 10 using control signals 60 and 61 from addition circuits 7 and 8.
Compare according to the following and output a signal if there is a difference.

The failure determination circuit 17 receives the outputs of the two expected value determination circuits 11 and 12, and creates and holds data indicating which memory block has a failure.

Further, as shown in FIG. 2, the failure detection data generation circuit 16 includes a data string selection register 40. address counter 4
1. It is composed of a data ROM 42. Data RO
Several types of data strings for failure detection are written in M42 in order to increase the failure detection rate, and selection thereof is performed by data set in the data string selection register 40. The data string selection register 40 is set by the CPU before executing memory failure detection.
It receives the data string selection data 44 given from 1 and outputs the start address of the selected data string by referring to an internal table. The address counter 41 receives this start address, adds the number of acknowledge signals 43 given from the DMA controller 2 to this address, and generates a read address for the data ROM 42. If the data string is composed of n pieces of data, the address counter that counts the acknowledge signal 43, which will be described later, is n
It is composed of a forward counter, and returns to 0 when the number of acknowledge signals 43 exceeds n. On the other hand, the adder circuit 7, as shown in FIG.
an addend register 50 which takes in by the write signal 55 from the DMA controller 2; an addend register 51 which holds the addition result before the timing; The output adder 52, the addition data number register 53 that holds the addition data number 58 from the CPUI, and the DMA acknowledge signal 57 from the DMA controller 2 are counted, and compared with the value of the addition data number register 53, it is determined that they match. The addition control circuit 54 outputs a reset signal 59 for the adder register 50 and a control signal 60 for the expected value determination circuit 11 when the addition is performed.

Next, the operation of the memory failure detection circuit shown in FIG. 1 will be explained.

When the information processing apparatus including the memory failure detection circuit according to the present invention is powered on, the CPU 1 executes a startup program including memory failure detection processing. In the program, initial settings of the memory failure detection circuit are performed, and these initial settings are roughly divided into two: data settings and status settings. Data setting is done in DMA
Controller 2. Memory selection register 13 and data string selection register 40 in failure detection data generation circuit 16
．． Addition data number register 53 for addition circuits 7 and 8. Expected value addition registers 9 and 10 each indicate the number of the memory block for which failure detection is to be performed, the number of data to be written to the memory block, the type of failure detection data to be written, the number of addresses at which the expected value is to be determined, and the expected value of data addition. The value is set.

The states of the buffers 64, 65, and 15 and the memory control circuit 14 are set, and all the buffers are set to an enabled state, and the memory control circuit 14 is set to a write permission output state. The data necessary for this initial setting is stored in a non-volatile memory (not shown) external to the CPU, but it is rewritable and
is not limited to this, as long as it is accessible.

When the initial settings are completed, the CPUI instructs the DMA controller 2 to start memory failure detection. In response to this request, the DMA controller 2 sends the data bus 18. After making a request for occupation of the address bus 19 and control bus 20 and granting approval, the CPU is disconnected from the bus until the right to use the bus is returned from the DMA controller 2. Furthermore, the memory control circuit 14 provides write permission signals 21 and 22 to the selected memory block based on memory specification data from the memory selection register 13. In this embodiment, a case is shown in which memory blocks 3 and 4 are selected.

When bus occupancy is permitted, the DMA controller 2 provides a read signal 45 to the data ROM 42 in the failure detection data generation circuit 16. The address counter 41 generates an address by adding the number of DMA acknowledge signals 43 given from the DMA controller 2 every time one piece of data is read from the data ROM 42 to the start address of the data string given from the data string selection register 40. Provided to data ROM 42.

The data ROM 42 receives the address and read signal 45 and outputs failure detection data.

This output data is sent to data bus 18 via enabled buffer 15 and buses 30 and 32 . They are simultaneously written to the same addresses in memory processors 3 and 4 through enabled buffer 64 and 65° buses 29 and 31. This memory address is created by a counter inside the DMA controller 2 and is given to each memory block 3 and 4 via an address bus 19.

When such an operation is repeated an initial set number of times, the DMA controller 2 returns the exclusive right of the bus to the CPU 1. At this time, if there is an area in the memory block where no data has been written yet, the write operation described above is repeated. In this case, it is necessary to set the DMA controller 2 from the CPU 1 so that the write address starts from the address following the last address of the last write.

When the writing of the failure detection data by DMA is completed, the CPU 1 disables the buffers 64 and 65, sets the memory control circuit 14 to a read permission signal output state, and sets data indicating the memory block to be read in the memory selection register 13. After that, press D again.
Instructs the MA controller 2 to start DMA.

The memory control circuit 14 sends read permission signals 21 and 2 to the memory block selected during writing.
Give 2. The failure detection data generating circuit 16 is supplied with a read signal 45 and a DMA acknowledge signal 43 from the DMA controller 2, as in the case of data writing, and outputs failure detection data. Data is read from each memory block 3 and 4 at the same time as the failure detection data is output, but since buffers 64 and 65 are disabled, the data from memory blocks 3 and 4 is input to adder circuits 7 and 8. Ru. Addition circuits 7 and 8 add the data read from memory blocks 3 and 4 by the number set in addition data number register 53, and output the result together with expected value determination timing signal 60.

Expected value determination circuits 11 and 12 are connected to adder circuits 7 and 8.
The addition results from the control signals 60 and 61 are compared with the values in the addition expected value registers 9 and 10, and if they do not match, the mismatch signals 25 and 26 are output to the defective determination circuit 17. The defect determination circuit 17 receives these mismatch signals 25 and 26 and holds data representing the memory block number where the failure occurred. After the failure detection is completed, this data is transferred to the data bus 1 by the read request signal 49 of the CPU 1.
8 to CPU1.

The table shown in FIG. 4 is a table showing the judgment results of the expected value judgment circuit based on the memory read data and the output results of the adder circuit.

In the example shown in FIG. 4, the addition expected value register 9 contains FFF.
Eh is 4h (=n
) is set. The expected value determination circuit 11 determines whether the memory is defective during a memory read operation for each value set in the addition data number setting register 53. Therefore, in the case shown in FIG. 4, failure determination is made when the read address of the memory block is
.

It is struck when 000Bh...

As an example, assume that there is a defective memory at memory address 0005h. At this time, as for the output of the adder 52, since the added value of the read data whose addresses are from ooooh to 0003h is equal to the expected value, the determination in this area is normal. However, in addresses 0004h to 0007h, since there is a memory defect at 0005h, the addition result and the expected value do not match, and the expected value determination circuit 11 determines that the memory is defective. Furthermore, in order to improve the failure detection rate, it is also possible to perform memory failure detection multiple times by changing the type of failure detection data.

FIG. 5 is a block diagram showing another embodiment of the present invention.

The embodiment shown in FIG. 1 uses the same number of adder circuits, expected addition value registers, and expected value judgment circuits as memory blocks, and in addition to writing data for failure detection, it also compares the written data with the expected addition value. , is performed simultaneously on all selected memory blocks, whereas in this embodiment, writing of fault detection data is performed simultaneously on all selected memory blocks, but addition of read data and Comparison of the addition result and expected addition value is performed by one addition circuit 7. Addition expected value register 9 and expected value judgment circuit 11
This is done for each memory block using . Since the read comparison is performed for each memory block, it is necessary to reset the value of the memory selection register 13 for each comparison process. Further, in this embodiment, the defect determination circuit 17 shown in FIG. 1 is not provided, and a method is adopted in which the mismatch signal of the expected value determination circuit 11 is directly returned to the CPU 1, but a defect determination circuit is provided as in FIG. It is clear that it is possible.

Furthermore, in this embodiment, a ROM 5 is connected as a type of memory block. The defectiveness of ROM5 can be determined by only reading comparison processing, and can be treated in the same way as other memory processors 3 and 4. However, since the data in ROM5 does not have a fixed pattern, Add.

The result of addition of all data in the ROM 5 is set as the expected value, and comparison with the result of addition is performed only once.

〔Effect of the invention〕

As described above, the memory failure detection circuit of the present invention uses a DMA controller to perform DMA transfer to a memory block targeted for failure detection and to write failure detection data at high speed. Furthermore, DMA transfer is also performed for reading data written in the memory to perform high-speed failure detection.

Furthermore, when detecting faults in large-capacity memories, it is possible to divide the memory into multiple memory blocks and simultaneously write data for fault detection into multiple memory blocks.
Also, instead of comparing written data and read data for all memories, it adds a certain number of memory data and determines the addition result and its expected value. This makes it possible to speed up memory failure detection.

Furthermore, by adding an adder circuit, an addition expected value register, and an expected value judgment circuit to each memory block in determining the data written to the memory, -times of DM
With A transfer, it is possible to detect failures in multiple memory blocks, and it is possible to increase the speed of the - layer.

Therefore, for devices such as workstations that require a memory failure detection function as an initial process after the device is powered on, and that memory failure detection processing needs to be executed in a short period of time, or for devices such as Since the circuit to be used is small-scale and low-cost, it is highly effective when applied to a memory failure detection circuit of a large-capacity memory board such as an expansion memory board.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the present invention, FIG. 2 is a block diagram showing an example of a pattern/data generation circuit, FIG. 3 is a block diagram showing an example of an adding circuit, and FIG. 5 is a table showing the principle of defect detection, and FIG. 5 is a block diagram showing another embodiment of the present invention. In the figure, 1...CPU, 2...DMA controller, 3.4...Memory block, 5...
...ROM. 7.8...Addition circuit, 9,10...Addition expected value register, 11.12...Expected value judgment circuit, 13...Memory selection register , 14...
...Memory control circuit, 15, 64, 65.
...Buffer, 16...Failure detection data generation circuit, 17...Failure judgment circuit, 18...
...Data bus, 19...Address bus,
20...Huntrolbus, 21.22...
...read/write signal, 25.26...mismatch signal, 29-34...bus, 40...
...Data string selection register, 41...Address counter, 42...Data ROM, 43...
...Acknowledge signal, 44...Data string selection data, 45.49...Read signal, 5.
... Addend register, 51 ... Addend register, 52 ... Adder, 53 ... Addition data number register, 54 ... Adder control circuit, 55...Write signal, 56...
...Read data, 58...Additional data number,
59...Reset signal, 60.61...
·Control signal. Agent: Patent Attorney Shinbian Uchihara 4th year

Claims (2)

[Claims] (1) In a system including a central processing unit (CPU) and a plurality of memory blocks connected to a bus included in the CPU, a memory failure detection circuit that detects failures in the memory blocks collects data for failure detection. a data generating means for generating data; a writing means for simultaneously writing the data into any plurality of memory blocks among the plurality of memory blocks; and from the plurality of memory blocks to which the data has been written; A reading means reads each memory block, an adding means adds the read data, and compares the addition result with a preset expected value at a constant cycle, and outputs a defect detection signal if they do not match. and a reset means that resets the addition means at the constant cycle. (2) The adding means, the comparing means, and the resetting means are provided for each of the plurality of memory blocks, and the reading means reads each memory block simultaneously from the plurality of memory blocks. A memory failure detection circuit according to claim 1.