JPS63199357U - - Google Patents
Info
- Publication number
- JPS63199357U JPS63199357U JP8676687U JP8676687U JPS63199357U JP S63199357 U JPS63199357 U JP S63199357U JP 8676687 U JP8676687 U JP 8676687U JP 8676687 U JP8676687 U JP 8676687U JP S63199357 U JPS63199357 U JP S63199357U
- Authority
- JP
- Japan
- Prior art keywords
- image memory
- point position
- specifying
- generating means
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Image Input (AREA)
Description
第１図は本実施例のイメージメモリ制御装置の
回路ブロツク図、第２図は本実施例のフレームメ
モリを含むシステムブロツク図、第３図〜第５図
は本実施例のイメージメモリ制御装置の動作を示
すタイムチヤートである。
３…ホストコンピユータ、５…ＣＰＵ、８…イ
メージメモリ部、１１〜１４，２０…Ｆ．Ｆ．、
１５，１６…カウンタ、１７，１８…比較器、１
９…デコーダ、２１，２２…セレクタ、２３…ビ
ツトマツプメモリ制御回路、２４…イメージメモ
リ。
FIG. 1 is a circuit block diagram of the image memory control device of this embodiment, FIG. 2 is a system block diagram including a frame memory of this embodiment, and FIGS. 3 to 5 are a circuit block diagram of the image memory control device of this embodiment. This is a time chart showing the operation. 3...Host computer, 5...CPU, 8...Image memory unit, 11-14, 20...F. F. ,
15, 16... Counter, 17, 18... Comparator, 1
9... Decoder, 21, 22... Selector, 23... Bit map memory control circuit, 24... Image memory.
Claims (1)
マツプ形式のイメージメモリの制御装置において
、 前記イメージメモリへ同一データを書込む領域
の始点位置と終点位置を指定する指定手段と、高
速クロツク発生手段と、該高速クロツク発生手段
より出力されるクロツク信号に同期して前記指定
手段により指定された前記始点位置から終点位置
までの所定ビツト毎のアドレスを順次出力するア
ドレス発生手段と、該アドレス発生手段の出力に
従つて前記イメージメモリへ同一データを書込む
書込み制御手段とを有することを特徴とするイメ
ージメモリ制御装置。[Claims for Utility Model Registration] A control device for a bitmap image memory capable of writing and reading image data, comprising: specifying means for specifying a starting point position and an ending point position of an area in which the same data is written to the image memory; a high-speed clock generating means; and an address generating means for sequentially outputting an address for each predetermined bit from the starting point position to the ending point position specified by the specifying means in synchronization with the clock signal output from the high-speed clock generating means; An image memory control device comprising write control means for writing the same data into the image memory according to the output of the address generation means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8676687U JPS63199357U (en) | 1987-06-05 | 1987-06-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8676687U JPS63199357U (en) | 1987-06-05 | 1987-06-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63199357U true JPS63199357U (en) | 1988-12-22 |
Family
ID=30943382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8676687U Pending JPS63199357U (en) | 1987-06-05 | 1987-06-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63199357U (en) |
-
1987
- 1987-06-05 JP JP8676687U patent/JPS63199357U/ja active Pending