JPS61162898U - - Google Patents
Info
- Publication number
- JPS61162898U JPS61162898U JP4775286U JP4775286U JPS61162898U JP S61162898 U JPS61162898 U JP S61162898U JP 4775286 U JP4775286 U JP 4775286U JP 4775286 U JP4775286 U JP 4775286U JP S61162898 U JPS61162898 U JP S61162898U
- Authority
- JP
- Japan
- Prior art keywords
- storage device
- musical instrument
- pulse counter
- memory switch
- rhythm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000033764 rhythmic process Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の第１実施例の構成を示す図、
第２図は第１図の動作説明用タイムチヤート、第
３図は本考案の他の実施例の主要構成図である。
ＣＬ…クロツクパルス発振器、ＣＮＴ…パルス
計数器、ＲＡＭ…記憶装置、ＭＳＷ―１〜ＭＳＷ
―４…メモリ開閉器、ＴＳＢ…バツフア、ＦＦ…
フリツプフロツプ回路、ＳＳＷ…スタート開閉器
、ＴＳ…音源回路、ＳＰ…スピーカ。
FIG. 1 is a diagram showing the configuration of the first embodiment of the present invention;
FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a main configuration diagram of another embodiment of the present invention. CL...Clock pulse oscillator, CNT...Pulse counter, RAM...Storage device, MSW-1 to MSW
-4...Memory switch, TSB...Buffer, FF...
Flip-flop circuit, SSW...start switch, TS...sound source circuit, SP...speaker.
Claims (1)
込が可能で、且つ書込・読出端子と書込制御端子
・読出制御端子とを有するランダムアクセス型記
憶装置と、 リズム演奏楽器と対応して設けられ前記記憶装
置に書込むため操作されるメモリ開閉器と、 前記のメモリ開閉器・パルス計数器間に挿入し
た論理回路と、 前記記憶装置の読出し出力により楽器音を発生
する音源回路とを具備し、 メモリ開閉器の操作によつて記憶装置に書込ま
れたリズムがパルス計数器の指定する所定時間経
過後より前記記憶装置から読出され楽器音を発生
すること を特徴とする自動リズム演奏装置。[Scope of Claim for Utility Model Registration] A random access storage device that is capable of reading and writing at an address designated by a pulse counter and has a write/read terminal, a write control terminal, and a read control terminal, and a rhythm. A memory switch provided corresponding to the musical instrument and operated to write data into the storage device; a logic circuit inserted between the memory switch and the pulse counter; and a sound source circuit that generates musical instrument sounds, and the rhythm written in the storage device by the operation of the memory switch is read out from the storage device after a predetermined time specified by the pulse counter and generates the musical instrument sound. Features an automatic rhythm performance device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4775286U JPS628078Y2 (en) | 1986-03-31 | 1986-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4775286U JPS628078Y2 (en) | 1986-03-31 | 1986-03-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61162898U true JPS61162898U (en) | 1986-10-08 |
| JPS628078Y2 JPS628078Y2 (en) | 1987-02-25 |
Family
ID=30563367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4775286U Expired JPS628078Y2 (en) | 1986-03-31 | 1986-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS628078Y2 (en) |
-
1986
- 1986-03-31 JP JP4775286U patent/JPS628078Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS628078Y2 (en) | 1987-02-25 |
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