JPS6331449U - - Google Patents
Info
- Publication number
- JPS6331449U JPS6331449U JP12376186U JP12376186U JPS6331449U JP S6331449 U JPS6331449 U JP S6331449U JP 12376186 U JP12376186 U JP 12376186U JP 12376186 U JP12376186 U JP 12376186U JP S6331449 U JPS6331449 U JP S6331449U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- circuit
- disk device
- data
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の一実施例を示す仮想デイスク
装置を含むシステム構成図、第２図は第１図のＲ
ＯＭデイスクユニツトの構成図、第３図は第１図
のＲＡＭデイスクユニツトの構成図である。
２０：ＲＯＭ、２１：デコーダ、２２：ＲＯＭ
デイスクユニツトＩ／Ｆ、２３：ライト回路、２
４：イレーズ回路、３０：ＲＡＭ、３１：デコー
ダ、３２：ＲＡＭデイスクユニツトＩ／Ｆ、３３
：リフレツシユ回路、３４：バツクアツプ回路。
FIG. 1 is a system configuration diagram including a virtual disk device showing an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing the configuration of the RAM disk unit shown in FIG. 1. 20: ROM, 21: Decoder, 22: ROM
Disk unit I/F, 23: Write circuit, 2
4: Erase circuit, 30: RAM, 31: Decoder, 32: RAM disk unit I/F, 33
: Refresh circuit, 34: Backup circuit.
Claims (1)
読み出し制御を行うメモリコントロール回路とを
有する仮想デイスク装置において、上位のデイス
クコントロール装置に接続するためのアドレスの
変換またはデータ形式の変換等を行う仮想デイス
クインタフエース回路を設けたことを特徴とする
仮想デイスク装置。 (2) 上記メモリをＲＯＭとし、上記メモリコン
トロール回路をデータの書き込みを行う書き込み
回路とデータの消去を行うイレーズ回路とで構成
することを特徴とする実用新案登録請求の範囲第
１項記載の仮想デイスク装置。 (3) 上記メモリをＲＡＭとし、上記メモリコン
トロール回路をリフレツシユ回路とバツクアツプ
回路とで構成することを特徴とする実用新案登録
請求の範囲第１項記載の仮想デイスク装置。[Scope of claims for utility model registration] (1) Memory and writing and writing of data to the memory
A virtual disk device having a memory control circuit that performs read control, characterized in that it is provided with a virtual disk interface circuit that converts addresses or data formats for connection to an upper disk control device. disk device. (2) A virtual utility model according to claim 1, wherein the memory is a ROM, and the memory control circuit is composed of a write circuit for writing data and an erase circuit for erasing data. disk device. (3) The virtual disk device according to claim 1, wherein the memory is a RAM, and the memory control circuit is composed of a refresh circuit and a backup circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12376186U JPS6331449U (en) | 1986-08-12 | 1986-08-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12376186U JPS6331449U (en) | 1986-08-12 | 1986-08-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331449U true JPS6331449U (en) | 1988-03-01 |
Family
ID=31015159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12376186U Pending JPS6331449U (en) | 1986-08-12 | 1986-08-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331449U (en) |
-
1986
- 1986-08-12 JP JP12376186U patent/JPS6331449U/ja active Pending
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