JPS6214521U - - Google Patents
Info
- Publication number
- JPS6214521U JPS6214521U JP10297985U JP10297985U JPS6214521U JP S6214521 U JPS6214521 U JP S6214521U JP 10297985 U JP10297985 U JP 10297985U JP 10297985 U JP10297985 U JP 10297985U JP S6214521 U JPS6214521 U JP S6214521U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- potential
- power supply
- vcc
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Power Sources (AREA)
- Static Random-Access Memory (AREA)
Description
第１図はこの考案の一実施例によるメモリ電源
回路を示す回路図、第２図は第１図におけるＲＡ
Ｍの各端子の電位変化を示す波形図、第３図は従
来のメモリ周辺回路を示す回路図、第４図は第３
図におけるＲＡＭの各端子の電位変化を示す波形
図である。
図において、Ｓはチツプセレクタ端子、Ｖｃｃ
は電源端子、Ｒ／Ｗは読出し／書込み制御端子、
Ｃ１，Ｃ３は時定数決定用コンデンサである。な
お、図中、同一符号は同一または相当部分を示す
。
FIG. 1 is a circuit diagram showing a memory power supply circuit according to an embodiment of this invention, and FIG. 2 is a circuit diagram showing the RA in FIG.
Figure 3 is a circuit diagram showing the conventional memory peripheral circuit; Figure 4 is a waveform diagram showing potential changes at each terminal of M.
FIG. 3 is a waveform diagram showing potential changes at each terminal of the RAM in the figure. In the figure, S is a chip selector terminal, Vcc
is the power supply terminal, R/W is the read/write control terminal,
C 1 and C 3 are time constant determining capacitors. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
読出し／書込み制御Ｒ／Ｗ端子を有するランダム
アクセスメモリＲＡＭ装置を動作させるための電
源回路において、供給電源の閉成ＯＮ時と開放Ｏ
ＦＦ時とで上記チツプセレクタ端子電位の変化時
定数を異ならしめ、上記ＯＮ時には上記Ｖｃｃ端
子及びＲ／Ｗ端子の電位が動作可能電位に達する
までに上記Ｓ端子の電位を非選択状態まで立上ら
せ、上記ＯＦＦ時には上記Ｖｃｃ端子及びＲ／Ｗ
端子の電位が動作不能状態に低下するまで上記Ｓ
端子の電位を非選択状態に保持するようにしたこ
とを特徴とするメモリ電源回路。 In a power supply circuit for operating a random access memory RAM device having a power supply Vcc terminal, a chip selector S terminal, and a read/write control R/W terminal, when the supply power is closed ON and when the supply power is opened O
The change time constant of the chip selector terminal potential is made different depending on when it is FF, and when it is ON, the potential of the S terminal is raised to a non-selected state before the potential of the Vcc terminal and the R/W terminal reach the operable potential. When the above is OFF, the above Vcc terminal and R/W
The above S until the terminal potential drops to an inoperable state.
A memory power supply circuit characterized in that the potential of a terminal is held in a non-selected state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10297985U JPS6214521U (en) | 1985-07-05 | 1985-07-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10297985U JPS6214521U (en) | 1985-07-05 | 1985-07-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6214521U true JPS6214521U (en) | 1987-01-28 |
Family
ID=30975117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10297985U Pending JPS6214521U (en) | 1985-07-05 | 1985-07-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214521U (en) |
-
1985
- 1985-07-05 JP JP10297985U patent/JPS6214521U/ja active Pending
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