JPH0374053U - - Google Patents
Info
- Publication number
- JPH0374053U JPH0374053U JP13321889U JP13321889U JPH0374053U JP H0374053 U JPH0374053 U JP H0374053U JP 13321889 U JP13321889 U JP 13321889U JP 13321889 U JP13321889 U JP 13321889U JP H0374053 U JPH0374053 U JP H0374053U
- Authority
- JP
- Japan
- Prior art keywords
- memory chip
- address
- card
- chip
- redundant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007547 defect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は従来のＩＣカードの一例のブロツク図である
。
１０１，１０２……外部のアドレス端子、１０
３……外部の端子、１０４，１０５……外部
のＶｐｐ端子、１０６，１０７，１０９，１１２
……メモリチツプ上のアドレス端子、１０８，１
１０，１１３……メモリチツプ上のＶｐｐ端子、
１１４，１１９，１２４……メモリチツプ上のＧ
ＮＤ端子、１１５，１２０，１２３……メモリチ
ツプ上のＶｃｃ端子、１１６，１１８，１２２…
…メモリチツプ上のＩ／Ｏ端子、１１７，１１１
，１２１……メモリチツプ上の端子、１２５
……外部のＶｃｃ端子、１２６……外部のＧＮＤ
端子、１２７……外部のＩ／Ｏ端子、１２８，１
２９……ＯＲ回路。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a block diagram of an example of a conventional IC card. 101, 102...external address terminals, 10
3...External terminal, 104, 105...External Vpp terminal, 106, 107, 109, 112
...Address terminal on memory chip, 108,1
10,113... Vpp terminal on memory chip,
114, 119, 124...G on memory chip
ND terminals, 115, 120, 123... Vcc terminals on the memory chip, 116, 118, 122...
...I/O terminals on memory chip, 117, 111
, 121...Terminal on memory chip, 125
...External Vcc terminal, 126...External GND
Terminal, 127...External I/O terminal, 128,1
29...OR circuit.
Claims (1)
カードにおいて、ユーザーがデータメモリとして
使用するメモリチツプと冗長用メモリチツプと、
前記メモリチツプの任意のアドレスに不備があつ
た場合、該アドレスが選択された時に限り前記冗
長用メモリチツプを代用として動作させる為の制
御用メモリチツプとを搭載する事を特徴とするＩ
Ｃカード。 IC equipped with programmed ROM chip
In the card, a memory chip used by the user as data memory and a redundant memory chip,
The device is characterized by being equipped with a control memory chip for operating the redundant memory chip as a substitute only when the address is selected if there is a defect in any address of the memory chip.
C card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13321889U JPH0374053U (en) | 1989-11-15 | 1989-11-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13321889U JPH0374053U (en) | 1989-11-15 | 1989-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0374053U true JPH0374053U (en) | 1991-07-25 |
Family
ID=31680629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13321889U Pending JPH0374053U (en) | 1989-11-15 | 1989-11-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0374053U (en) |
-
1989
- 1989-11-15 JP JP13321889U patent/JPH0374053U/ja active Pending
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