JPH0175400U

JPH0175400U -

Info

Publication number: JPH0175400U
Application number: JP1987171074U
Authority: JP
Priority date: 1987-11-09
Filing date: 1987-11-09
Publication date: 1989-05-22

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すダイナミツク
メモリＩＣのブロツク回路図、第２図は第１図の
ダイナミツクメモリＩＣにおいて識別コードを読
み出す際における当該ダイナミツクメモリＩＣの
各部信号のタイミングチヤート、第３図は第１図
実施例における識別コードの意味付けの一例を示
す図である。１…ＩＤ情報ＲＯＭ、２…メモリセル、３…ク
ロツクジエネレータ、４…アドレスバツフア、５
…ロウデコーダ、６…カラムデコーダ、７…セン
スアンプ・Ｉ／Ｏバツフア、８…ＩＤ端子、９…
クロツク端子、１０…クロツク端子
、１１…アドレス端子、１２…出力端子。 FIG. 1 is a block circuit diagram of a dynamic memory IC showing an embodiment of the present invention, and FIG. 2 is a timing diagram of signals of various parts of the dynamic memory IC shown in FIG. 1 when reading out an identification code. FIG. 3 is a diagram showing an example of the meaning of the identification code in the embodiment of FIG. 1. 1... ID information ROM, 2... memory cell, 3... clock generator, 4... address buffer, 5
...Row decoder, 6...Column decoder, 7...Sense amplifier/I/O buffer, 8...ID terminal, 9...
Clock terminal, 10...Clock terminal, 11...Address terminal, 12...Output terminal.

Claims

[Scope of utility model registration request]

In a dynamic memory IC that has a clock terminal, a clock terminal, and an identification code readout terminal, and can write to a memory cell at any time and read from the memory cell at any time, the manufacturer and manufacturer A read-only memory is provided for storing an identification code of at least one of a mask or a manufacturing lot, and when the identification code read terminal is in a first logic state, an operation to write to or read from the memory cell is provided. A dynamic memory IC characterized in that, if the identification code read terminal is in a second logic state, the identification code is read out.