JPH0394698U - - Google Patents
Info
- Publication number
- JPH0394698U JPH0394698U JP353990U JP353990U JPH0394698U JP H0394698 U JPH0394698 U JP H0394698U JP 353990 U JP353990 U JP 353990U JP 353990 U JP353990 U JP 353990U JP H0394698 U JPH0394698 U JP H0394698U
- Authority
- JP
- Japan
- Prior art keywords
- logic element
- signal
- inputs
- outputs
- access request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
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- Dram (AREA)
Description
第1図は本考案回路の一実施例の構成を示す接
続図、第2図はその作用説明用タイムチヤート、
第3図は従来回路の一例の構成を示す接続図、第
4図はその作用説明用タイムチヤートである。
1……第1(フリツプフロツプ)論理素子、2
……第2(ノア)論理素子、3……第3(否定)
論理素子、4……第4(フリツプフロツプ)論理
素子、5……第5(フリツプフロツプ)論理素子
。
Fig. 1 is a connection diagram showing the configuration of one embodiment of the circuit of the present invention, Fig. 2 is a time chart for explaining its operation,
FIG. 3 is a connection diagram showing the configuration of an example of a conventional circuit, and FIG. 4 is a time chart for explaining its operation. 1...first (flip-flop) logic element, 2
...2nd (Noah) logic element, 3...3rd (negation)
Logic element, 4...Fourth (flip-flop) logic element, 5...Fifth (flip-flop) logic element.
Claims (1)
ロツク信号CLKを入力して行、列アドレス切替
用制御信号S2を出力する第1論理素子1と、メ
モリアクセス要求信号S1とこの第1論理素子1
の出力信号S2を入力してリード、ライト共通の
制御信号S3を出力する第2論理素子2と、クロ
ツク信号CLKを入力して否定信号S0を出力す
る第3論理素子3と、メモリアクセス要求信号S
1とこの第3論理素子3の出力信号S0を入力し
てリード時の制御信号S4を出力する第4論理素
子4と、上記論理素子1の出力信号S2とクロツ
ク信号CLKを入力してライト時の制御信号S5
を出力する第5論理素子5とよりなるダイナミツ
クランダムアクセスメモリ制御回路。 A first logic element 1 which inputs a memory access request signal S1 and a clock signal CLK of a required frequency and outputs a row/column address switching control signal S2 , and a memory access request signal S1 and this first logic element 1.
a second logic element 2 which inputs an output signal S2 and outputs a control signal S3 common to read and write; a third logic element 3 which inputs a clock signal CLK and outputs a negation signal S0 ; Access request signal S
1 and a fourth logic element 4 which inputs the output signal S0 of the third logic element 3 and outputs the control signal S4 at the time of reading, and inputs the output signal S2 of the logic element 1 and the clock signal CLK. Control signal S when writing
A dynamic random access memory control circuit comprising a fifth logic element 5 which outputs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP353990U JPH0394698U (en) | 1990-01-19 | 1990-01-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP353990U JPH0394698U (en) | 1990-01-19 | 1990-01-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0394698U true JPH0394698U (en) | 1991-09-26 |
Family
ID=31507354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP353990U Pending JPH0394698U (en) | 1990-01-19 | 1990-01-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0394698U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009056285A (en) * | 2007-08-06 | 2009-03-19 | Marubishi Baioenji:Kk | Excrement collector |
-
1990
- 1990-01-19 JP JP353990U patent/JPH0394698U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009056285A (en) * | 2007-08-06 | 2009-03-19 | Marubishi Baioenji:Kk | Excrement collector |
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