JPH0513359B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sense amplifier system for a semiconductor memory device.

[Technical background of the invention]

FIG. 2 shows a part of a typical configuration example of a conventional dynamic RMA (random access memory). That is, 1 is an input address buffer into which an address signal is input, 2 is a refresh address generator that generates a refresh address signal, 3 is an address multiplexer, LR is a row decoder line,
RD ₁ , RD ₂ , RD ₃ , RD ₄ ... are row decoders,
WL ₁ , WL ₂ , WL ₃ , WL ₄ ... are word lines, MC ₁ ,
MC ₂ , MC ₃ , MC ₄ ... are memory cells, BL,
are bit lines, DMC ₁ and DMC ₂ are dummy memory cells, DWL ₁ and DWL ₂ are dummy word lines, SA is a sense amplifier, LS is a sense latch control signal line, SE
is the sense signal, Q _B and _B are the column decoders (CD)
In the bit line selection transistor controlled by the output, DL is the data line, 4 is the output circuit, C _B is the capacitance of the bit line, and _CR is the capacitance of the row decoder line.

Each of the memory cells MC ₁ ... consists of one capacitor C _S and one transfer gate Q, and stores information "0" or "1" depending on whether charge is stored in the capacitor C _S or not. It is something to remember. However, the charge accumulated in the capacitor C _S usually decreases over time due to leakage or the like. Therefore, it is necessary to read the stored charge once and write it again before it completely disappears to accumulate the charge again.
This operation is called refresh, and the above refresh operation is generally required in dynamic RMA.
RAM has the restriction that all memory cells must be refreshed once every 4ms.

FIG. 3 shows the sequence of operations in a memory configured to perform the above-mentioned refresh periodically, and normal read/write operations cannot be performed during the refresh period. This is because, for example, when refreshing a certain memory cell _MC1 , this
This is because it is not possible to read data from other memory cells connected to the bit line BL used for the operation of _MC1 . Therefore,
In computer systems using RAM,
During the period when RAM is being refreshed
Even when you want to access RAM, the RAM cannot be used, so you have to wait before accessing the RAM during the refresh period, which equivalently increases the time it takes to access the RAM, which is a hindrance to speeding up the process. That's a problem.

Here, the operation of the dynamic RAM will be briefly described with reference to the timing waveforms shown in FIG. A cycle of memory operation begins when an address signal input changes or a chip enable signal (not shown) is input. First, bit line BL,
When BL is precharged and then, for example, word line WL ₁ is selected by the above address signal input, this word line WL ₁ and the dummy word line
DWL ₁ becomes high level, and the memory cell MC ₁ and dummy cell connected to them
Each transfer gate Q of DMC ₁ opens, and the respective stored information appears on the bit line BL, and a minute potential difference is generated between the bit lines BL and BL. Next, when the sense signal SE is activated, the sense amplifier
SA operates and senses and amplifies the potential difference between bit lines BL and BL. At this point the memory cell
Since MC ₁ remains selected by word line WL ₁ , bit line BL remains selected after the above sense operation.
The information stored in memory cell _MC1 is refreshed by the potential. At the same time, the information on bit line BL is transmitted to data line DL via bit line selection transistors _QB and _B. This data line DL,
The information read out to DL undergoes waveform shaping etc. in the output circuit 4, and output data _Dput is obtained with a considerable delay from the sensing operation.

Dynamic RAM that involves a refresh operation as described above has the disadvantage that it is difficult to use because it imposes a burden on the user of having to be conscious of the refresh timing when designing the system product. on the other hand,
Dynamic RAM usually has a memory cell area 1/4 of that of static RAM that does not involve a refresh operation, so it has the advantage of being suitable for high density storage and being inexpensive.

Therefore, although the above-mentioned refresh operation is involved, the normal operation and the refresh operation are performed in a time-sharing manner so that the user does not need to be aware of it, that is, so that the user can use it as if it were static RAM. virtual statistics
RAM is proposed. This virtual static
An overview of the operation in the RAM will be explained with reference to FIG. This operation differs from the operation described above with reference to FIG. 4 in that (1) the selected word line (for example, WL ₁ ) and a predetermined dummy word line (for example, DWL ₁ ) are driven in a pulsed manner; (2) The sense amplifier SA is driven in a pulsed manner by the sense signal SE to sense the potential difference generated between the bit lines BL and (3) The data sensed by the sense amplifier SA is sent to the output circuit 4. The bit line BL is once precharged to its original state during the period from 1 to 1 until it is completely output, and after a short delay it is connected to a word line other than the selected word line WL ₁ (for example,
WL ₃ ) and a given word line (e.g. DWL ₂ )
The data in the memory ML ₃ which is selectively driven by the word line WL ₃ is read out in a pulsed manner, and the sense amplifier SA is again driven in a pulsed manner by the SE signal to sense the potential difference between the bit lines. This means that the memory cell _MC3 is rewritten (refreshed). Note that the data of the memory cell _MC3 where this refresh is performed does not need to be output from the output circuit 4.
This refresh operation is performed relatively quickly.
That is, in the operation shown in FIG. 5, the refresh operation of another memory cell is completed in parallel with the normal access operation. Note that in the above operation example, cell selection for refresh operation is performed after cell selection for normal access operation, but conversely, even if it were performed earlier in time, it would not have too much of a negative impact on normal operation. does not occur. In addition, in the above operation example, the refresh operation is completely completed before the read data from the normal access operation is output from the output circuit 4, but if the refresh operation takes a little longer, the normal access If it is determined that the virtual static method, in which the user does not see (or does not need to worry about) the refresh operation, has a great advantage, even if it increases the time required, this method can be adopted. Further, the time it takes for the word line selected for the refresh operation to return to the unselected state may be longer than the time it takes for the word line selected in the normal access operation to return to the unselected state. . Further, in the above operation example, word line selection is performed twice within one memory cycle to perform refresh, but refresh does not necessarily have to be performed for each cycle. This is because refreshing only needs to be performed once for each memory cell within a fairly long period of time, and the above operation example is for a memory cell MC that happens to share the bit and line BL with the memory cell MC ₃ to be refreshed. Since this is the case where ₁ is accessed, the word line is selected twice within one cycle. If this is not the case, that is, if the RAM is not being accessed when the refresh is attempted, it is sufficient to simply perform the refresh.

By the way, since there is a delay associated with the large stray capacitance _CD in the data line DL, it takes quite a long time to drive it by the sense amplifier SA, and the data line DL is driven. During this time, the sense amplifier SA cannot move on to the next job (refresh operation in the above example). If the sense amplifier SA operates slowly as described above, the cycle time will become slow if the sense amplifier SA is operated more than once in one cycle as described above.

In order to solve this problem, a latch circuit is provided on the output side of the sense amplifier as shown in Figure 6, and while this latch circuit is driving the output circuit, the sense amplifier is isolated from the latch circuit. A sense amplifier system capable of performing refresh operations independently was proposed in a patent application filed in 1983 by the applicant.
- Proposed by No. 163508. This sense amplifier system will be explained in detail below with reference to FIG. FIG. 6 schematically shows a part of the semiconductor memory integrated circuit, and shows SA ₁₁ to SA ₁₄ , ... and
SA ₂₁ to SA ₂₄ , .
are connected to the bit line pairs BL ₁₁ , ₁₁ to _{BL 12} , ₁₂ , . . . and BL ₂₁ , ₂₁ to BL ₂₄ , ₂₄ , . Similarly to BL, a plurality of memory cells of a memory cell block and one dummy cell are connected. LA ₁₁ is a latch circuit and is arranged between the sense amplifiers SA ₁₁ and SA ₁₂ ,
The above sense amplifier SA ₁₁ is connected to the latch input terminal,
Switch circuits S ₁₁ and SA ₁₂ are provided to control connection switches between each output terminal of SA ₁₂ . In the same way as above, sense amplifier SA ₁₃ ,
A latch circuit LA ₁₂ and switch circuits S ₁₃ and S ₁₄ are provided corresponding to SA ₁₄ , and sense amplifiers SA ₂₁ and
A latch circuit LA ₂₁ and switch circuits S _{21 and} S 22 are provided corresponding to SA ₂₂ , and sense amplifiers SA ₂₃ and
A latch circuit LA ₂₂ and switch circuits S ₂₃ and S ₂₄ are provided corresponding to SA ₂₄ .

On the other hand, 2BL ₁ , 2 ₁ are the bit lines BL ₁₁ ,
_{BL 11} to BL _{14 , 14 , .}
~BL ₂₄ , ₂₄ , . . . are the second bit line pairs provided in parallel on both sides. The above bit line pair 2BL,
2BL ₁ and the latch circuit located inside it
A switch circuit 2S ₁₁ , _{2S 12} , ... for controlling the connection between each latch output terminal of LA ₁₁ , _{12 ,} ... by controlling the output of a row system decoder.
... are provided, and the bit line pair 2BL ₂ , 2
BL ₂ and the latch circuit LA ₂₁ located inside it,
Switch circuits 2S ₂₁ , 2S ₂₂ , . . . are provided for controlling connections between the latch output terminals of LA ₂₂ , .

_2SA1 is a second sense amplifier connected to the second bit line pair _2BL1 , ₂₁ , and is connected to the data line pair DL via a switch circuit _2S1 . Similarly, _2SA2 is a second sense amplifier connected to the second bit line pair _2BL2 , ₂₂ , and is connected to the data line pair DL via a switch circuit _2S2 . 4 is an output circuit connected to the data line pair DL, C _B , C _2B , C _D
are the wiring capacitances.

Next, an example of the operation of the above memory will be explained. During a normal read operation, for example, the bit line pair
When sensing the information of BL ₁ , ₁ , first the above information is sensed and amplified by the sense amplifier SA ₁₁ . At this time, the above sense amplifier SA ₁₁ and the latch circuit
The switch circuit S 11 between the latch circuit LA ₁₁ and the switch circuit S ₁₁ may be closed or open, but the other switch circuits S ₁₂ and 2S ₁₁ connected to the latch circuit LA ₁₁ are open, and at the latest the sense amplifier SA ₁₁ When the sensing operation is completed, the switch circuit _S11 is closed and the data of the sense amplifier _SA11 is transferred to the latch circuit _LA11 and latched. After this, even if the switch circuit SA ₁₁ is opened, the latch circuit LA ₁₁ latches the data. Then, the switch circuits 2S ₁₁ and 2S ₁ close, and the latch circuit LA ₁₁ connects the second bit line pair 2BL ₁ , 2 ₁ and the data lines DL,
is driven, and the information on the bit lines 2BL, ₂₁ is sensed and amplified by the second sense amplifier _2SA1 . The output of the sense amplifier _2SA1 is read out to the output circuit 4 via the switch circuit _2S1 and the data line pair DL.

In the above operation, in order for the latch circuit CA ₁₁ to drive the second bit lines 2BL ₁ and 2 ₁ , the large wiring capacitances C _B and _CD must be charged and discharged, which increases the required time. However, even when this latch circuit LA ₁₁ is driving the second bit lines 2BL ₁ and 2 ₁ and the data line DL, the switch circuit S ₁₁ between this latch circuit LA ₁₁ and the sense amplifier SA ₁₁ is If you open it, the above sense amplifier SA ₁₁
can be operated freely without adversely affecting the data line DL. Therefore, if the normal read data is first sensed by the sense amplifier SA ₁₁ and then latched to the latch circuit CAB ₁₁ ,
When this latch circuit LA ₁₁ is disconnected from the sense amplifier SA ₁₁ by the switch circuit S ₁₁ , the sense amplifier SA ₁₁ operates for the next refresh of the memory cell connected to the bit line BL ₁₁ or ₁₁ . I can do it. That is, the latch circuit
The second bit line 2BL ₁ , where LA ₁₁ is heavily loaded,
The above refresh operation can be fully incorporated while driving the data line _2BL1 and the data line DL.

By the above-described operation, the sense amplifier SA ₁₁ can be used once for a normal read operation and once for a refresh operation during one cycle. in this case,
During reflex operation, the sense amplifier SA ₁₁
Since there is no need to read out the data read out to the output circuit 4, there is no need to transfer the data of the sense amplifier _SA11 to the latch circuit _CA11 . Further, the output circuit 4 normally has a latch function and latches only the read data for the normal operation.

FIG. 7 shows a representative example of a part of the bit line group, sense amplifier group, latch circuit group, and switch circuit group. Here, the sense amplifier SA ₁₁ consists of a CMOS type sense amplifier including a drive transistor controlled by a pair of sense signals SE, and similarly a latch circuit LA _11.
The switch circuit S11 is composed of a CMOS type latch circuit including a drive transistor controlled by a pair of latch signals LE, the switch circuit _S11 is composed of an N-channel transistor controlled by a switch signal _φ1 , and the switch circuit _2S11 is a CMOS type latch circuit including a drive transistor controlled by a pair of latch signals _LE , It is controlled by an N-channel transistor.

Note that the sense amplifier system as described above is not limited to a memory that performs a normal read operation and a refresh operation during one cycle as described above, but can also be used for a general memory for the purpose of increasing the speed of a sense amplifier. That is, in this case, the first sensor operation during one cycle is used for reading data by accessing the first address,
After latching this first read data, while transmitting it from the data line to the output circuit, the sense amplifier is disconnected from the latch circuit and left free, and then used for data read by the second address access. You may. In this way, the sensing of the subsequent data is completed during the signal delay on the data line, so pipeline-like or parallel control is possible, and for the second read data, It looks as if the sense time is zero. In other words, high-speed operation is possible when reading several consecutive pieces of data.

[Problems with background technology]

However, with the configuration of the sense amplifier system as described above, although it is possible to achieve high-speed read operations, the chip area increases significantly due to the provision of the latch circuit. For example, the length is about 12mm,
Assuming a design rule of 1.2 μm on a chip with a width of about 6 mm, the calculated length of one sense amplifier is about 70 μm, and the length of the latch circuit is about 150 μm (sense amplifier, latch circuit). each has a width of no more than one column). If the first bit line is divided into, for example, 16 parts in the length direction, 16 sense amplifiers and 8 latch circuits are required in the length direction within one column.
Therefore, the length occupied by the latch circuits in the chip length direction is approximately 150 μm x 8 pieces = 1.2 mm, or approximately 10% of the total length. This means that the cost of the chip increases by about 10% due to the latch circuit.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
The present invention provides a sense amplifier system for a semiconductor memory device that reduces the area occupied on a chip without impairing the high speed of read operations.

[Summary of the invention]

That is, the sense amplifier system of the semiconductor memory device of the present invention has first and second first amplifiers extending in the column direction.
a latch circuit disposed between the first bit line group and the second first bit line group; and a latch circuit disposed between the first bit line group and the latch circuit. a first sense amplifier group, which is arranged respectively, one end of which is connected to one of the first bit line groups, and the other end of which is connected to the latch circuit via a switch; A second sense is disposed between the bit line group and the latch circuit, and has one end connected to one of the second first bit line group and the other end connected to the latch circuit via a switch. A memory cell section having a group of amplifiers,
Multiple units are arranged in the column direction. Further, a second bit line is provided adjacent to each memory cell section, extending in the column direction, and connected to a latch circuit in each memory cell section via a switch.

According to the above structure, a plurality of memory cell sections are arranged in the column direction, and the second bit line is long. However, the latch circuit in each memory cell section is connected to the first and second latch circuits of the memory cell section.
Since the sensor is located close to the sense amplifier, the information read operation can be speeded up. Also,
A plurality of sense amplifiers are arranged adjacent to the latch circuit in the column direction, and each sense amplifier is shared by the latch circuit. Moreover, since the second bit line is shared by a plurality of memory cell sections in the column direction, the area occupied by the latch circuit and the second bit line on the chip can be reduced.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, as described above with reference to FIG. 6, a latch circuit is connected to the sense amplifier via a switch circuit, and a second bit line pair is connected to this latch circuit via another switch circuit. 6 shows a part of a semiconductor memory configured as shown in FIG.
The difference is that the latch circuit is shared between the two columns, but otherwise they are almost the same.

That is, in the sense system shown in Figure 1, BL ₁₁ ,
BL ₁₁ , BL ₁₂ , ₁₂ are the divided first bit line pairs in one column, and the first bit line pairs in the other three columns that share the latch circuit LA ₁₁ with this column are BL ₂₁ , ₂₁ . (BL ₄₂ ,
BL ₄₂ ). _SA11 to _SA42 are sense amplifiers connected to the first bit line pairs _BL11 , ₁₁ to _BL42 , _42, respectively. S ₁₁ to _{S 42} are switch circuits controlled by the outputs of column and row decoders so as to selectively connect the sense amplifiers SA ₁₁ to _{SA 42} to the latch circuit LA ₁₁ at predetermined timings. In another set of four columns provided next to the above-mentioned set of four columns, the first bit line pair
BL ₅₁ , ₅₁ ~ BL ₃₂ , ₃₂ , sense amplifier SA ₅₁ ~
SA ₃₂ , switch circuits S ₅₁ to S ₃₂ and latch circuit LA ₂₁ are provided.

Note that the first bit line pair has, for example, 16 bit lines in the length direction.
In the case of division, eight latch circuits are provided in the length direction in the same manner as above, but illustration thereof is omitted for simplicity of explanation.

Further, between the two sets of four columns, a second bit line pair 2 is connected parallel to the first bit line pair.
BL ₁ , 2 ₁ are provided, and this second bit line pair 2 BL ₁ , 2 ₁ is shared by two sets of adjacent columns in order to reduce the total number of bit lines, and each pair of bit lines 2BL 1 , 2 1 is shared by two sets of adjacent columns. latch circuit in
LA ₁₁ , LA ₂₁ (only one of each is shown)
and the second bit line pair 2BL ₁ , 2 ₁ are selectively switch-controlled switch circuits 2S ₁₁ , 2
S ₂₁ (only one set of each is shown) is provided correspondingly. In this case, the switch circuits 2S ₁₁ and 2S ₂₁ output one of the column-system decoder outputs related to column selection within the set of columns to which they belong, and one of the plurality of latch circuits in the set of columns. It is controlled by an output obtained by performing a logical product with a row-related decoder output for selecting a latch circuit.

The second bit line pair 2BL ₁ , 2 ₁ is connected to the data line pair DL via a switch 2S ₁ which is controlled by the column decoder output. A circuit D _io and an output circuit D _put are connected.

The operation of the sense amplifier system described above is such that the sense amplifier output side switch circuits between each other are selectively controlled so that each sense amplifier in a set of adjacent columns shares one latch circuit, and As described above with reference to FIG. 6, except that the output side switch circuits of the latch circuits between the latch circuits are selectively controlled so that the latch circuits of the columns of the set share the second bit line pair of the set. The operation is almost the same, and high-speed read operations can be obtained.

Considering the area occupied by the sense amplifier system on the chip according to the above embodiment, by sharing one latch circuit in four columns, the area occupied by the latch circuit is approximately 1/
It decreases to 4. In this case, the pattern shape of the latch circuit is 4 times the row direction and 1/4 the column direction.
By doing so, the chip length can be shortened. For example, if eight columns share one latch circuit, the area occupied by the latch circuit is reduced to about 1/8, and in the case of Figure 6, the latch circuit occupies about 10% of the entire chip area. If the above latch circuit is shared, the total area of the chip will be 10% x 7/
This will result in a decrease of about 8.

Furthermore, in the sense amplifier system of the above embodiment, the number of second bit line pairs is also reduced as one latch circuit is shared by a plurality of columns. For example, if there are 512 columns on one chip, 512 second bit line pairs are required in the case of Figure 6, but one latch circuit is shared by eight columns, and When one set of second bit line pairs is provided correspondingly, it is sufficient to provide 64 sets (=512×1/8) of second bit line pairs, and the second bit line pairs of each set are
The switch circuit group on the latch circuit output side between the bit line pair and the latch circuit group may be controlled by the output of the row system decoder. Here, a set of second
If the line width of the bit line pair is about 7 μm,
In the sense amplifier system of the above embodiment, the chip width can be reduced by about 7 .mu.m.times.(512-64).apprxeq.3.1 mm compared to the case of FIG. 6. This value enables a very large reduction in chip width compared to the overall width of the chip, which is about 6 mm, and brings about a very large cost reduction effect. Moreover, in the sense amplifier system of the above embodiment, two adjacent columns share one second bit line pair, so the number of second bit line pairs is further halved, making it possible to further shorten the chip width. It is.

〔Effect of the invention〕

As described above, according to the sense amplifier system of the semiconductor memory device of the present invention, a latch circuit is provided for latching the output of the sense amplifier, and the latch circuit is shared by the sense amplifiers of multiple columns, so that the read operation can be performed at high speed. The area occupied on the chip can be reduced without sacrificing performance, making it suitable for use in large capacity memories.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the sense amplifier system of the semiconductor memory device of the present invention, FIG. 2 is a configuration explanatory diagram showing a part of a conventional semiconductor memory, and FIG. 3 is the memory of FIG. 2. FIG. 4 is a diagram showing an example of the operation of the memory in FIG. 2, and FIG. 5 is a diagram showing the time relationship between normal operation and refresh operation in the memory shown in FIG. 2. FIG. FIG. 6 is a timing diagram showing an example of the operation of the semiconductor memory device according to the earlier application of the present application, and FIG.
FIG. 2 is a circuit diagram specifically showing a part of the circuit shown in the figure. BL ₁₁ , ₁₁ to BL ₃₂ , ₃₂ ...Bit line, 2
BL ₁ , 2 ₁ ... second bit line, SA ₁₁ to SA ₃₂ ...
... sense amplifier, S ₁₁ to _{S 32} ... sense amplifier output side switch circuit, 2S ₁₁ , 2S ₂₁ ... latch circuit output side switch circuit, LA ₁₁ , LA ₂₁ ... latch circuit.

Claims (1)

[Scope of Claims] 1. First and second first bit line groups extending in the column direction, and arranged between the first first bit line group and the second first bit line group. a latch circuit arranged between the first bit line group and the latch circuit, one end of which is connected to one of the first bit line groups, and the other end connected to one of the first bit line groups through a switch. a first sense amplifier group connected to the latch circuit; and a first sense amplifier group arranged between the second first bit line group and the latch circuit, one end of which is connected to one of the second first bit line groups. and a second sense amplifier group whose other end is connected to the latch circuit via a switch, a plurality of memory cell parts are arranged in the column direction, and each memory cell part has a position adjacent to the second sense amplifier group. A semiconductor memory device comprising: a second bit line extending in the column direction and connected to a latch circuit in each memory cell portion via a switch. 2 A plurality of the memory cell parts are arranged in the row direction, and the second bit line is arranged between the latch circuits of the first and second memory cell parts adjacent to each other in the row direction, and the second bit line is arranged between the latch circuits of the first and second memory cell parts adjacent to each other in the row direction. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to the latch circuits in the first and second memory cell portions through the respective latch circuits. 3 After the first information sensed by the first and second sense amplifier groups of each of the memory cell sections is latched by the latch circuit of the memory cell section, the latch circuit and the first and second sense amplifier groups The method of the present invention is characterized in that the switch between the above-mentioned memory cells is turned off, and the control is then performed so that the first and second sense amplifier groups in each of the memory cell sections can sense the second information. The semiconductor memory device according to scope 1. 4. A patent characterized in that the first information is read from the memory cell by a normal read operation, and the second information is read from the memory cell by a refresh operation. A semiconductor memory device according to claim 3. 5. A switch circuit is arranged between the second bit line and the first and second latch circuits of each memory cell section so that the second bit line is shared by the plurality of memory cell sections. A semiconductor memory device according to claim 1, characterized in that: