JPS62182775U - - Google Patents
Info
- Publication number
- JPS62182775U JPS62182775U JP7154086U JP7154086U JPS62182775U JP S62182775 U JPS62182775 U JP S62182775U JP 7154086 U JP7154086 U JP 7154086U JP 7154086 U JP7154086 U JP 7154086U JP S62182775 U JPS62182775 U JP S62182775U
- Authority
- JP
- Japan
- Prior art keywords
- verification
- card
- control means
- code
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012795 verification Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Credit Cards Or The Like (AREA)
Description
第１図〜第６図は本考案の１実施例によるＩＣ
カードを示すもので、第１図は機能ブロツク図、
第２図ａおよびｂはＩＣカード側および親機側の
システム構成をそれぞれ示すブロツク図。第３図
はＥＥＰ―ＲＯＭのメモリエリアを示すマツプ図
、第４図〜第６図はＩＣカード内のマイクロコン
ピユータ用プログラムの要部フローチヤート図で
あり、第４図はメインルーチンを、また第５図は
予備照合サブルーチンを、第６図は照合サブルー
チンをそれぞれ示すフローチヤート図。
１……ＩＣカード、４……ＲＯＭ、５……Ｉ／
Ｏポート、７……ＥＥＰ―ＲＯＭ、１０……親機
、１ｃ，１０ｃ……シリアル通信端子、２０……
秘密コードメモリエリア、３０……照合連続失敗
カウンタエリア、４０……カードデイゼーブル情
報記憶エリア、５０……予備照合コード記憶エリ
ア、６０……データメモリエリア。
1 to 6 are ICs according to one embodiment of the present invention.
This shows the card, and Figure 1 is a functional block diagram.
FIGS. 2a and 2b are block diagrams showing the system configurations of the IC card side and the base unit side, respectively. Fig. 3 is a map showing the memory area of the EEP-ROM, Figs. 4 to 6 are flowcharts of the main parts of the microcomputer program in the IC card, and Fig. FIG. 5 is a flowchart showing a preliminary verification subroutine, and FIG. 6 is a flowchart showing a verification subroutine. 1...IC card, 4...ROM, 5...I/
O port, 7...EEP-ROM, 10...Base unit, 1c, 10c...Serial communication terminal, 20...
Secret code memory area, 30... Continuous verification failure counter area, 40... Card disable information storage area, 50... Preliminary verification code storage area, 60... Data memory area.
Claims (1)
記憶手段に記憶されるデータの書込みおよび読出
し等のアクセスを制御するためのデータ処理制御
手段とを有し、前記記憶手段はカードアクセスツ
ールの正当性を判定するための秘密コードを記憶
する秘密コードメモリエリアと、ＩＣカード自体
が無効状態にあることを示すデータを記憶するた
めのカードデイゼーブル情報記憶エリアとを含み
、前記データ処理制御手段は前記秘密コードに対
応してカードアクセスツール側よりＩＣカードに
与えられる照合対象データと前記秘密コードとの
間の照合を判定する照合判定手段と、該照合判定
手段による照合に失敗したときに、前記カードデ
イゼーブル情報記憶エリアにカードの無効化を示
すデータを記憶書込みするためのカードデイゼー
ブル書込み制御手段とを含んで成るＩＣカードに
おいて、前記記憶手段は予備照合用コードを記憶
するための予備照合コード記憶エリアを含み、前
記データ処理制御手段は前記予備照合コードに対
応してカードアクセスツール側よりＩＣカードに
与えられる予備照合用データと前記予備照合コー
ドとの間の照合を判定する予備照合判定手段と、
該判定結果に従つて前記照合判定手段に前記照合
対象データと前記秘密コードとの間の照合の実行
を許可する照合制御手段とを含んでいることを特
徴とするＩＣカード。 It has a storage means made of a non-volatile semiconductor memory, and a data processing control means for controlling access such as writing and reading of data stored in the storage means, and the storage means is configured to check the validity of the card access tool. The data processing control means includes a secret code memory area for storing a secret code for determination, and a card disable information storage area for storing data indicating that the IC card itself is in an invalid state. a verification determination means for determining verification between the verification target data given to the IC card from the card access tool side in response to the secret code and the secret code; An IC card comprising a card disable write control means for storing and writing data indicating invalidation of the card in a disable information storage area, the storage means having a reserve for storing a preliminary verification code. The data processing control means includes a verification code storage area, and the data processing control means performs preliminary verification for determining verification between the preliminary verification data given to the IC card from the card access tool side in response to the preliminary verification code and the preliminary verification code. A determination means,
An IC card characterized by comprising a verification control means for permitting the verification determination means to perform verification between the verification target data and the secret code according to the determination result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7154086U JPH0726775Y2 (en) | 1986-05-13 | 1986-05-13 | IC card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7154086U JPH0726775Y2 (en) | 1986-05-13 | 1986-05-13 | IC card |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62182775U true JPS62182775U (en) | 1987-11-19 |
| JPH0726775Y2 JPH0726775Y2 (en) | 1995-06-14 |
Family
ID=30914186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7154086U Expired - Lifetime JPH0726775Y2 (en) | 1986-05-13 | 1986-05-13 | IC card |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0726775Y2 (en) |
-
1986
- 1986-05-13 JP JP7154086U patent/JPH0726775Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0726775Y2 (en) | 1995-06-14 |
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