JPS62157275U - - Google Patents
Info
- Publication number
- JPS62157275U JPS62157275U JP4601486U JP4601486U JPS62157275U JP S62157275 U JPS62157275 U JP S62157275U JP 4601486 U JP4601486 U JP 4601486U JP 4601486 U JP4601486 U JP 4601486U JP S62157275 U JPS62157275 U JP S62157275U
- Authority
- JP
- Japan
- Prior art keywords
- card
- information storage
- storage area
- control means
- disable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012795 verification Methods 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Credit Cards Or The Like (AREA)
Description
第１図〜第１０図は、本考案の１実施例による
ＩＣカードを示すもので、第１図は機能ブロツク
図、第２図ａおよびｂはＩＣカード側および親機
側のシステム構成をそれぞれ示すブロツク図。第
３図はＥＥＰ―ＲＯＭのメモリエリアを示すマツ
プ図、第４図はカードデイゼーブル情報記憶エリ
アおよび補助デイゼーブル情報記憶エリアのビツ
トマツプ図。第５図および第６図はＩＣカード内
のマイクロコンピユータ用プログラムの要部フロ
ーチヤート図であり、第５図はメインルーチンを
、また第６図は照合サブルーチンをそれぞれ示す
フローチヤート図。
１……ＩＣカード、４……ＲＯＭ、５……Ｉ／
Ｏポート、７……ＥＥＰ―ＲＯＭ、１０……親機
、１ｃ，１０ｃ……シリアル通信端子、２０……
秘密コードメモリエリア、３０……照合連続失敗
回数カウンタエリア、４１……カードデイゼーブ
ル情報記憶エリア、４２……補助デイゼーブル情
報記憶エリア。
Figures 1 to 10 show an IC card according to an embodiment of the present invention. Figure 1 is a functional block diagram, and Figures 2a and 2b show the system configurations of the IC card side and base unit side, respectively. Block diagram shown. FIG. 3 is a map diagram showing the memory area of the EEP-ROM, and FIG. 4 is a bit map diagram of the card disable information storage area and the auxiliary disable information storage area. 5 and 6 are flowcharts of main parts of the microcomputer program in the IC card, with FIG. 5 showing the main routine and FIG. 6 showing the verification subroutine, respectively. 1...IC card, 4...ROM, 5...I/
O port, 7...EEP-ROM, 10...Main unit, 1c, 10c...Serial communication terminal, 20...
Secret code memory area, 30...Continuous verification failure count counter area, 41...Card disable information storage area, 42...Auxiliary disable information storage area.
Claims (1)
記憶手段に記憶されるデータの書込みおよび読出
し等のアクセスを制御するためのデータ処理制御
手段とを有し、前記記憶手段は秘密コードを記憶
する秘密コードメモリエリアと、ＩＣカード自体
が無効状態にあることを示すデータを記憶するた
めのカードデイゼーブル情報記憶エリアとを含み
、前記データ処理制御手段は前記秘密コードに対
応して外部よりＩＣカードに与えられる照合対象
データと前記秘密コードとの間の照合を判定する
照合判定手段と、該照合判定手段による照合が所
定の連続回数に渡つて失敗したときに、前記カー
ドデイゼーブル情報記憶エリアにカードの無効化
を示すデータを記憶書込みするためのカードデイ
ゼーブル書込み制御手段とを含んで成るＩＣカー
ドにおいて、前記記憶手段は前記カードデイゼー
ブル情報記憶エリアとは別に設けられた補助デイ
ゼーブル情報記憶エリアを含み、前記データ処理
制御手段は前記補助デイゼーブル情報記憶エリア
にカードの無効化を示すデータを記憶書込みする
ための補助デイゼーブル書込み制御手段と、前記
カードデイゼーブル情報記憶エリアと前記補助デ
イゼーブル情報記憶エリアの両方の記憶内容に基
づいてカードの無効性を検出する無効カード検出
手段を含んでいることを特徴とするＩＣカード。 It has a storage means made of a nonvolatile semiconductor memory, and a data processing control means for controlling access such as writing and reading data stored in the storage means, and the storage means has a secret code for storing a secret code. the data processing control means includes a memory area and a card disable information storage area for storing data indicating that the IC card itself is in an invalid state; a verification determination means for determining verification between given verification target data and the secret code; and a verification determination means for determining verification between the given verification target data and the secret code; and a card disable write control means for storing and writing data indicating invalidation of the card, wherein the storage means has auxiliary disable information provided separately from the card disable information storage area. the data processing control means includes an auxiliary disable write control means for storing and writing data indicating invalidation of the card in the auxiliary disable information storage area; the card disable information storage area and the auxiliary disable information storage area; An IC card characterized by comprising invalid card detection means for detecting invalidity of the card based on the stored contents of both information storage areas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4601486U JPH054056Y2 (en) | 1986-03-28 | 1986-03-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4601486U JPH054056Y2 (en) | 1986-03-28 | 1986-03-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62157275U true JPS62157275U (en) | 1987-10-06 |
| JPH054056Y2 JPH054056Y2 (en) | 1993-02-01 |
Family
ID=30865286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4601486U Expired - Lifetime JPH054056Y2 (en) | 1986-03-28 | 1986-03-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH054056Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0233691A (en) * | 1988-07-25 | 1990-02-02 | Nippon Telegr & Teleph Corp <Ntt> | Ic card |
-
1986
- 1986-03-28 JP JP4601486U patent/JPH054056Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0233691A (en) * | 1988-07-25 | 1990-02-02 | Nippon Telegr & Teleph Corp <Ntt> | Ic card |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH054056Y2 (en) | 1993-02-01 |
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