JPS62157274U - - Google Patents
Info
- Publication number
- JPS62157274U JPS62157274U JP1986046013U JP4601386U JPS62157274U JP S62157274 U JPS62157274 U JP S62157274U JP 1986046013 U JP1986046013 U JP 1986046013U JP 4601386 U JP4601386 U JP 4601386U JP S62157274 U JPS62157274 U JP S62157274U
- Authority
- JP
- Japan
- Prior art keywords
- section
- data
- writing
- attribute area
- invalidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013502 data validation Methods 0.000 claims 1
- 238000012986 modification Methods 0.000 claims 1
- 230000004048 modification Effects 0.000 claims 1
- 238000010200 validation analysis Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
Description
第１図〜第１０図は、本考案の１実施例による
ＩＣカードを示すもので、第１図は機能ブロツク
図、第２図ａおよびｂはＩＣカード側および親機
側のシステム構成をそれぞれ示すブロツク図。第
３図はＥＥＰ―ＲＯＭのメモリエリアを示すマツ
プ図、第４図はフアイルデイレクトリエリアを示
すマツプ図、第５図はフアイルエリアを示すマツ
プ図。第６図〜第１０図は、ＩＣカード内のマイ
クロコンピユータ用プログラムの要部フローチヤ
ート図であり、第６図はメインルーチン、第７図
はフアイル作成サブルーチン、第８図はフアイル
オープンサブルーチン、第９図は書込みサブルー
チン、第１０図はフアイル抹消サブルーチンをそ
れぞれ示すフローチヤート図。
１……ＩＣカード、４……ＲＯＭ、５……Ｉ／
Ｏポート、７……ＥＥＰ―ＲＯＭ、１０……親機
、１ｃ，１０ｃ……シリアル通信端子、２０……
フアイルデイレクトリエリア、２３……フアイル
ヘツダー先頭アドレス。
Figures 1 to 10 show an IC card according to an embodiment of the present invention. Figure 1 is a functional block diagram, and Figures 2a and 2b show the system configurations of the IC card side and base unit side, respectively. Block diagram shown. FIG. 3 is a map diagram showing the memory area of the EEP-ROM, FIG. 4 is a map diagram showing the file directory area, and FIG. 5 is a map diagram showing the file area. Figures 6 to 10 are flowcharts of the main parts of the microcomputer program in the IC card. Figure 6 is the main routine, Figure 7 is the file creation subroutine, Figure 8 is the file open subroutine, and Figure 8 is the file open subroutine. FIG. 9 is a flowchart showing a write subroutine, and FIG. 10 is a flowchart showing a file deletion subroutine. 1...IC card, 4...ROM, 5...I/
O port, 7...EEP-ROM, 10...Base unit, 1c, 10c...Serial communication terminal, 20...
File directory area, 23...File header start address.
Claims (1)
段に記憶されるデータの書込みおよび読出し等の
アクセスを制御するためのデータ処理制御手段と
を有し、前記記憶手段が複数個のセクシヨンより
成るデータメモリエリアを有するとともに、前記
セクシヨンの番号を指定することにより、各セク
シヨンごとに独立してデータの書込みおよび読出
しを行なえるように構成されたＩＣカードにおい
て、前記各セクシヨンはそれぞれセクシヨン属性
エリアを含んで成り、かつ前記データ処理制御手
段は、前記セクシヨン内へのデータの記憶書込み
に伴つて当該セクシヨン属性エリアに所定のデー
タ有効化マークを記憶書込みするセクシヨン有効
化手段と、外部よりＩＣカードに与えられる指定
に基づいて前記セクシヨン属性エリア内に所定の
データ無効化マークを記憶書込みするためのセク
シヨン無効化手段と、前記セクシヨン属性エリア
に前記無効化マークがない場合には、当該セクシ
ヨンのデータの消去および／または修正を禁止す
るデータ抹消制御手段とを含んでいることを特徴
とするＩＣカード。 A data memory comprising a storage means comprising an EEP-ROM and a data processing control means for controlling access such as writing and reading of data stored in the storage means, the storage means comprising a plurality of sections. In an IC card having an area and configured such that data can be written and read independently for each section by specifying a number of the section, each section includes a section attribute area. and the data processing control means includes section validation means for storing and writing a predetermined data validation mark in the section attribute area as data is stored and written in the section; a section invalidation means for storing and writing a predetermined data invalidation mark in the section attribute area based on a specification, and erasing and erasing the data of the section if the invalidation mark does not exist in the section attribute area; An IC card characterized in that it includes a data erasure control means that prohibits modification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986046013U JPH089795Y2 (en) | 1986-03-28 | 1986-03-28 | IC card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986046013U JPH089795Y2 (en) | 1986-03-28 | 1986-03-28 | IC card |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62157274U true JPS62157274U (en) | 1987-10-06 |
| JPH089795Y2 JPH089795Y2 (en) | 1996-03-21 |
Family
ID=30865284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986046013U Expired - Lifetime JPH089795Y2 (en) | 1986-03-28 | 1986-03-28 | IC card |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH089795Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013109714A (en) * | 2011-11-24 | 2013-06-06 | Nippon Telegr & Teleph Corp <Ntt> | Portable recording medium, control method for portable recording medium and control program for portable recording medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5977699A (en) * | 1982-10-25 | 1984-05-04 | Dainippon Printing Co Ltd | Integrated circuit card |
| JPS5987568A (en) * | 1982-11-12 | 1984-05-21 | Dainippon Printing Co Ltd | Ic card |
-
1986
- 1986-03-28 JP JP1986046013U patent/JPH089795Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5977699A (en) * | 1982-10-25 | 1984-05-04 | Dainippon Printing Co Ltd | Integrated circuit card |
| JPS5987568A (en) * | 1982-11-12 | 1984-05-21 | Dainippon Printing Co Ltd | Ic card |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013109714A (en) * | 2011-11-24 | 2013-06-06 | Nippon Telegr & Teleph Corp <Ntt> | Portable recording medium, control method for portable recording medium and control program for portable recording medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH089795Y2 (en) | 1996-03-21 |
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