JPH01121199U - - Google Patents
Info
- Publication number
- JPH01121199U JPH01121199U JP1720388U JP1720388U JPH01121199U JP H01121199 U JPH01121199 U JP H01121199U JP 1720388 U JP1720388 U JP 1720388U JP 1720388 U JP1720388 U JP 1720388U JP H01121199 U JPH01121199 U JP H01121199U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- semiconductor memory
- detector
- detects
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
Description
第１図は本考案の第１の実施例のブロツク図、
第２図は電源投入後プリセツトされるメモリセル
を示す回路図、第３図は第１図のＩＣパツケージ
の平面図、第４図は第２の実施例のブロツク図、
第５図は第４図に示す疑似メモリクリア回路のタ
イムチヤート、第６図は従来の第１の例を示すブ
ロツク図、第７図は従来の第２の例を示すブロツ
ク図である。
１……不揮発性ＲＡＭ、２……電圧レベル検出
回路、３……モード・コントロール回路、４……
メモリクリアスイツチ、７……ＩＣパツケージ、
８……フリツプフロツプ、９……疑似メモリクリ
ア回路、１０……データバスプルアツプ回路、１
１……パワーオン検出回路。
FIG. 1 is a block diagram of the first embodiment of the present invention.
2 is a circuit diagram showing memory cells that are preset after power is turned on, FIG. 3 is a plan view of the IC package of FIG. 1, and FIG. 4 is a block diagram of the second embodiment.
5 is a time chart of the pseudo memory clear circuit shown in FIG. 4, FIG. 6 is a block diagram showing a first conventional example, and FIG. 7 is a block diagram showing a second conventional example. 1...Nonvolatile RAM, 2...Voltage level detection circuit, 3...Mode control circuit, 4...
Memory clear switch, 7...IC package,
8...Flip-flop, 9...Pseudo memory clear circuit, 10...Data bus pull-up circuit, 1
1...Power-on detection circuit.
Claims (1)
おいて、高電圧を含む三値の電圧レベルを検出す
る検出器と、その検出結果によつて読出し、書込
みを禁止する回路とを含むことを特徴とするバツ
クアツプ電源付き半導体メモリ。 A semiconductor memory having a backup power supply, characterized in that it includes a detector that detects three voltage levels including high voltage, and a circuit that prohibits reading and writing based on the detection result. semiconductor memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1720388U JPH01121199U (en) | 1988-02-10 | 1988-02-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1720388U JPH01121199U (en) | 1988-02-10 | 1988-02-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01121199U true JPH01121199U (en) | 1989-08-16 |
Family
ID=31230775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1720388U Pending JPH01121199U (en) | 1988-02-10 | 1988-02-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01121199U (en) |
-
1988
- 1988-02-10 JP JP1720388U patent/JPH01121199U/ja active Pending
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