JPH01188937A - Device mode switching system - Google Patents

Abstract

PURPOSE:To reduce a ROM space while using a conventional software by providing a ROM storing a program common to systems and another ROM storing a program of each system and switching both ROMs in the same address space. CONSTITUTION:A 1st system is selected when a system switch signal is equal to 0 and a 1st buffer 13 is enable. A CPU 1 is reset in the same way as the application of a power supply and outputs an address FFFFO(H) to an address bus 5. Thus a ROM address decoding circuit 6 transmits a decoding signal and a selection signal is sent to a 1st system ROM 3 through a terminal 13c. Then a system ROM 3 is made access. In such a way, the ROM 3 outputs data to the CPU 1 and therefore the CPU 1 serves as the 1st system. When the system switch signal is equal to 1, a 2nd system ROM 4 is made access. Thus the CPU 1 serves as the 2nd system.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device that shares two or more device modes, and particularly relates to an R device that stores a system-common program.
This relates to an OM switching method.

[Conventional technology]

Conventionally, in this type of device mode switching system, a program common to all systems was also stored in a ROM for each system.

[Problem to be solved by the invention]

In the conventional device mode switching method described above, a common program for each system was stored in the ROM of each system.
The location of the program in the ROM is different from the previous system ROM, which has the disadvantage that software that references the program in the ROM does not work in conventional software, and the RQM space in the memory space becomes large. .

[Means to solve the problem]

The device mode switching method of the present invention includes an address decoding means for decoding a common ROM storing a program common to the system and a system ROM storing a program for each system in a common address space; The system ROM is equipped with a switching means for switching the system ROM, and is configured to switch in the same address space.

[Effect]

Since the device mode switching method of the invention can be performed in the same address space, conventional software can be used as is, and the ROM space within the memory space can be reduced.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a device mode switching system according to the present invention. In the figure, 1 is a CPU that operates as a first system or a second system and outputs a write signal from a terminal 1a, and 2 is a common system RO in which system common programs such as initial settings are stored.
M13 is a first system RoM in which the program of the first system is stored, 4ti is a second system ROM in which the program of the second system is stored, 5 is an address bus, and 6 is an address from this address bus 5 to the terminal 6a. is input, and the address space FOOOO(H) ~ FFFFF(
ROM address decoder which decodes up to H) and outputs the decoded signal from the output terminal 6b, 7 is a data bus, 8
9 is a signal line to which a hardware reset signal is sent when the power is turned on, data from the data bus γ is input to the terminal 9a, a sea address from the address bus 5 is input to the terminal 9b, and a write signal is input to the terminal 9C. A reset control circuit in which a hardware reset signal is input to the terminal 9d, a reset signal for the CPU 1 is outputted from the terminal 9e, and a software reset signal is outputted from the terminal 9f.When 10 is "0", the first system is selected; 1", a signal line through which a system switching signal is sent so that the second system is selected; 11 is a signal line through which a software reset signal is input to the terminal 11a, a hardware reset signal is input to the terminal 11b, and a system switching signal is input to the terminal 11c. A switching circuit 12 receives a signal and outputs a buffer enable signal for each system ROM from terminals 11d, 11e, and 11f for switching between the first system and the second system; 12 has a decode signal input to a terminal 12a; terminal 12
An enable signal is input to b when enabled, and terminal 12
A common buffer 13 outputs a select signal to the common system ROM 2 from e, a decode signal is input to a terminal 13a, an enable signal is input to a terminal 13b when enabled, and a select signal is output from a terminal 13c to the first system ROM 2.
The first buffer 14 outputs to M3, a decode signal is input to the terminal 14a, an enable signal is input to the terminal 14b when enabled, and a select signal is input to the second buffer from the terminal 14c.
This is a second buffer output to the system ROM4.

Note that the common ROM2. 1st ROM3 and 2nd ROM4
The address space is F'0OOOO(H) to FFFF in common.
Let it be F (H). However, (H) indicates a hexadecimal number.

Next, the operation of the device mode switching method with the above configuration will be explained with reference to the flowchart shown in FIG. First, in step 81, the signal! ! 8, a nodeware reset signal is input to the terminal 9d of the reset control circuit 9 and the terminal 11b of the switching circuit 11, respectively, when the power is turned on. Then, in step S2, the switching circuit 11 operates when a hardware reset signal is input to its terminal 11b, and an enable signal is output from its terminal 11d to the terminal 12b of the common buffer 12.

Therefore, the common buffer 12 is enabled by inputting the enable signal. On the other hand, the reset control circuit 9
operates upon input of the above-mentioned no-ware reset signal, and outputs the reset signal to the CPU 1 from its terminal 9e.

Therefore, the CPU 1 is reset by inputting this reset signal, and the address FF is placed on the address bus 5.
Outputs FF0 (H) to the ROM address decode circuit 6. Therefore, the CPU Ia is reset (by inputting this reset signal) and outputs the address FFFF0 (H) on the address bus 5 to the ROM address decode circuit 6. Therefore, this ROM address decode circuit 6 decodes this address FFFF0 (H) and outputs a decoded signal from its terminal 6b. At this time, since the common buffer 12 is enabled, the terminal 12
The decoded signal inputted to the terminal a is directly output from the terminal 12c to the common system ROM 2 as a select signal. Therefore, in step S3, this common system ROM 2 is accessed and data is output to the CPU 1 via the data bus 7. Accordingly, in step S4, the system common program stored in the common system ROM 2 is operated by the CPU 1. Then, in step 85, when the operation of the system common program is finished, the first system ROM3 and the second system ROM
I10 with CPU1 due to a program outside of storage in 4.
A software reset command is output to the terminal 9c of the reset control circuit 9 at the address. The reset control circuit 9 operates upon input of this software reset command, and outputs a reset signal to the CPUI from its terminal 9e, and also outputs a shiftware reset signal to the switching circuit 11 from its terminal 9f. For this reason, switching circuit 1
1 is a common buffer 1 that operates when a software reset signal is input to its terminal 11a and outputs it from the terminal 11d.
If the system switching signal inputted to the terminal 11c via the signal line 10 is "0", the enable signal of the first buffer 13 outputted from the terminal 11e is enabled, and this system switching signal is disabled. If is "1", the enable signal of the second buffer 14 outputted from the terminal 11f is enabled.

Here, when the system switching signal is "O", the first buffer 1
3 is enabled, the first system is selected in step S6.

Then, when the CPU 1 is reset in the same way as when the power is turned on, it outputs the address FFFF0 (H) onto the address bus 5. Therefore, the ROM address decoding circuit 6 decodes this address F'FFFO(H) and outputs it to the terminal 6b.
outputs a decoded signal. Here, since the system 1 is selected, the first buffer 13 is enabled, and the select signal is output from the terminal 13C to the first system ROM 3. Therefore, in step S7, the first system RQM3 is accessed by inputting this select signal. In this way, the first system R
Since QM3 outputs data to CPU1, CPU1 can operate as the first system. In addition, in the same manner, the system switching signal is set to "1".
”, the second system RQM4 is accessed and C
PU1 can operate as a second system.

In addition, although the above explanation has been given for the case where there are two device modes, that is, the first system and the second system, the present invention is not limited to this, and the same can be done in the case where there are three or more device modes. Of course.

〔Effect of the invention〕

As explained in detail above, the device mode switching method according to the present invention is capable of switching in the same address space by providing an R (li) that stores a program common to the system and a ROM that stores a program for each system. Additionally, conventional software can operate as is, and the ROM space within the memory space can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the device mode switching method according to the present invention, and FIG. 2 is a flowchart for explaining the operation of FIG. 1. 1...◆CPU, 2...Kushi common system ROM, 3
...Hibiki 1st system ROM, 4...2nd system ROM, 5...address bus, 6.3@-ROM address decoder, 7...data bus, 8...signal line, 9...reset control circuit, 10...signal line, 11...switching circuit, 12...common buffer, 13e...first buffer, 14...second Batsuhua. Patent applicant NEC Corporation Japan [Engineering floor type company

Claims (1)

[Claims] In a device having two or more device modes, an address decoding means for decoding a common ROM storing a program common to the system and a system ROM storing a program for each system in a common address space; and a switching means for switching the system ROM.