JPH0652010A - Testing circuit - Google Patents

Abstract

PURPOSE:To facilitate the change of instruction data and to eliminate the restriction of a test item due to the capacity by changing the test ROM of a single chip microcomputer from a mask ROM to a RAM. CONSTITUTION:A RAM 5 capable of writing arbitray instruction data from a port at the time of test mode is provided, a selective circuit 8 for selecting the data of the RAM 5 instead of the data of a user ROM 2 and outputting them to an instruction decoder circuit 7 is provided and a test mode setting circuit 6 for executing control at the time of test mode is provided on the testing circuit for executing an operation confirmation by other instruction than that of the user ROM 2 of a single chip microcomputer. In such a manner the test of different items can by executed many times without minding the restriction of the capacity by the same sample.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit, and more particularly to a test capable of confirming the operation by an arbitrary instruction other than the user ROM in a test mode of a single chip microcomputer (microcomputer) operating by the user ROM. Regarding the circuit.

Here, the user ROM refers to a read only memory that stores user command data. RA
M is a random access memory capable of writing arbitrary data from the port in mode 1.

[0003]

2. Description of the Related Art Conventionally, in a test circuit of a single-chip microcomputer for confirming the operation by an arbitrary instruction other than a user ROM, as shown in FIG. 3, a user ROM 21 storing instruction data of the user and this user ROM 21. User ROM address setting circuit 20 that indicates the address of the test ROM 22 and a test ROM 22 that stores arbitrary command data to confirm the operation of the single-chip microcomputer in the test mode.
And a test RO indicating the address of this test ROM 22.
M address setting circuit 23 and user ROM 21 in normal times
Output signal of the test ROM21
Selection circuit 25 for selecting the output signal of
It has an instruction decoder circuit 24 that decodes the output signal from 5 and outputs an instruction signal for operating the single-chip microcomputer, and a test mode setting circuit 26 that switches between the normal mode and the test mode.

[0004]

In such a conventional test circuit, since the instruction data for confirming the operation of the single chip microcomputer is constituted by the ROM by an arbitrary instruction other than the user ROM, the test ROM is used. The data of could not be changed. Further, since the ROM has a limited number of instruction steps, the test items for operation confirmation must be designed in consideration of capacity.

The object of the present invention is to solve the above-mentioned problems,
It is to provide a test circuit that can easily change instruction data.

[0006]

A test circuit according to the present invention comprises a user ROM storing instruction data of a user,
A user ROM address setting circuit indicating the address of the user ROM, a RAM capable of writing data from a port in the test mode, a RAM address setting circuit indicating the address of the RAM, and a RAM address setting circuit for the user ROM in the normal mode. An output signal is selected, and in the test mode, a selection circuit for selecting and outputting the output signal of the RAM, and a command signal for decoding the signal from the selection circuit and operating the single-chip microcomputer are output. An instruction decoding circuit and a test mode setting circuit for switching between the test mode and the normal mode are provided.

[0007]

1 is a block diagram showing a test circuit according to an embodiment of the present invention. In FIG. 1, a RAM is used in this embodiment.
5, RAM address setting circuit 4 is used, and write enable signal 9 from test mode setting circuit 6 is RAM
5 is different from FIG. 3 in that it is applied to No. 5, and other parts are the same as in FIG.

In the normal mode, the address of the user ROM 2 is indicated by the user ROM address setting circuit 1, and the user ROM 2 outputs the instruction data corresponding to the address to the selection circuit 8. The selection circuit 8 outputs the signal from the user ROM 2 to the instruction decoder circuit 7, and the instruction signal output from the instruction decoder circuit 7 causes the single-chip microcomputer to operate.

In the test mode, the test mode setting circuit 6 outputs the RAM write enable signal 9 and the RAM 5 writes arbitrary instruction data from the port 3 to the address indicated by the RAM address setting circuit 4. After writing necessary instruction data, the test mode setting circuit 6 outputs the test signal 10, the selection circuit 8 outputs the signal from the RAM 5 to the instruction decoder circuit, and the instruction signal output from the instruction decoder circuit 7 , Single-chip microcomputer works.

In the test mode in which the test signal 10 is output, the port 3 operates in the same manner as in normal operation.

Next, FIG. 2 is a block diagram showing a test circuit of another embodiment of the present invention. In FIG. 2, the user ROM / RAM address setting circuit 11 of the present embodiment is the one in which the user ROM address setting circuit 1 of the above embodiment is also used as the RAM address setting circuit 4. Therefore, the addresses of both the user ROM 12 and the RAM 15 are indicated by the user ROM / RAM address setting circuit 11. The other operations are the same as those in the above-described first embodiment, and are omitted.

[0012]

As described above, according to the present invention, the user R
Since the instruction data is stored in the RAM in order to check the operation of the single-chip microcomputer by an arbitrary instruction other than OM, the instruction data can be easily changed, and the RAM data can be rewritten by the same single-chip microcomputer. This has the effect that multiple test items can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a test circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a test circuit of another embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional test circuit.

[Explanation of symbols]

 1,20 User ROM address setting circuit 2,12,21 User ROM 3,13 Port 4 RAM address setting circuit 5,15,22 RAM 6,6,26 Test mode setting circuit 7,17,24 Instruction decoder circuit 8,18 , 25 selection circuit 9, 19 RAM write enable signal 10, 14, 27 test signal 11 user ROM / RAM address setting circuit 23 test ROM address setting circuit

Claims (2)

[Claims] 1. A user ROM storing user instruction data, and a user R indicating an address of the user ROM.
The OM address setting circuit, the RAM capable of writing data from the port in the test mode, the RAM address setting circuit indicating the address of the RAM, and the output signal of the user ROM in the normal mode to select the test. In the mode, a selection circuit for selecting and outputting the output signal of the RAM, an instruction decoding circuit for decoding the signal from the selection circuit and outputting an instruction signal for operating a single-chip microcomputer, and the test mode And a test mode setting circuit for switching between the normal mode and the normal mode. 2. The user ROM and RAM are user ROs.
2. The test circuit according to claim 1, wherein the address is received from a circuit which also serves as an M address setting circuit and a RAM address setting circuit.