JPS5839322A - Data processor - Google Patents

Abstract

PURPOSE:To optionally select a starting address after the resetting of a CPU by providing an ROM which allows the CPU to send a different address signal to a data bus when a selector outputs an address signal indicating some address. CONSTITUTION:A selector 3 is equipped with input terminal groups 3B1-3B4 where an address signal for indicating the 1st address is inputted from the address signal output terminal ADR of a CPU1, and input terminal groups 3B1- 3B4 where an address signal for indicating the 2nd address is inputted. Then when the CPU1 sends out an address signal for specifying the zero address and the selector 3 outputs the address signal for the 2nd address, the CPU1 outputs data for instructing the transmission of the address signal for indicating the 1st address from an ROM5 to the data bus.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device such as a central processing unit (hereinafter referred to as a CPU), and relates to a data processing device such as a central processing unit (hereinafter referred to as a CPU), and a special data processing system that enables a start address to be arbitrarily selected when executing an instruction after a reset state of the CPU. A processing device is provided.

Generally, in a data processing device including a CPU, the CPU is reset when the power is turned on so that execution starts from a certain instruction regardless of whether the execution of the instruction is stopped or not. Therefore, when a reset force is applied to the CPU, the contents of the program counter that designates one of the addresses where each instruction is stored are set to zero, and the start address is normally set to zero.

As is well known, the CPU receives an address signal and a data bus from a read only memory (hereinafter referred to as ROM).
The above-mentioned instructions are stored in this ROM Ic. Therefore, a start instruction that the CPU starts executing immediately after the start is written in address zero of this ROM. When the CPU is reset, it sets the contents of the program counter to zero as described above, sends an address signal specifying the zero address in the ROM, and transfers the data corresponding to the instruction written to the zero address from the ROM. is sent to the data bus.

The CPU takes in the data on this data bus and decodes it.

An instruction based on this decoding result is executed.

By the way, in recent years, in order to increase the flexibility of programs, random access memory (hereinafter referred to as "random access memory"), which can be written and read, has been developed, instead of using the area starting from address zero as the ROM area for data to be written. It has been proposed to designate RAM1 [琥] for the RAM (referred to as RAM).

However, even if the CPU sends an address signal specifying the zero address to the address bus after the reset state Ill, no information has been written to the RAM at this point, so
The CPU stops operating at this point. For this reason, K, which is responsible for giving the first command to be executed to the CPH after the reset condition deafness, has the disadvantage of requiring a very complicated external circuit.

An object of the present invention is to provide a data processing device that can operate a CPU with a simple circuit configuration even if the area whose first address is zero is used as a RAM area.

In order to achieve such an object, one aspect of the present invention is to send an address signal representing a second address from a selector to an address bus after a reset state, and to use this as a part of an address signal representing a zero address sent from the CPU.

When the ROM is supplied with both address signals representing the second address, the CPU sends a command to the data bus to send an address signal representing the first address, and detects the address signal representing the fal address. In response to the output signal of the decoder, the selector switches from an address signal representing the second address to outputting an address signal that is outputted multiple times by the CPU.

The present invention will be described in detail below using the drawings.

The figure is a block diagram showing one embodiment of the present invention.

In the figure, 1 is the CPU, and the set input terminal R
When a reset signal is received from an external device (not shown), an address signal representing the contents of address zero is sent from the output terminal ADR to address bus inputs BO to input B15, and addresses 180 to 180 of address bus ABO to input 815 are sent. The 8-bit portion of the input BT is supplied to the decoder 2. This decoder 2 is e
When the decoder selection signal from the output terminal rORQ of f'U1 is supplied, the address signal supplied from the address bus is decoded, and this address signal represents the first address predetermined for the decoder 2. If it is an address signal, an output signal is generated at the output terminal 21 of the decoder 2.

In this case, since the address signal representing the first address is other than the zero address, when the CPUI is sending out the address signal representing the zero address, the output terminal 2 of the decoder 2
No sK output occurs.

On the other hand, the second input terminal group 3A1 to 344 of the selector 3 is at voltage ■. . is supplied to the second input terminal group 3Bl to 38.
4 is connected to the CPU 1 via address bus inputs AB12 to 815 among address bus inputs BO to AB15.

The switching signal terminal 3c is connected to the output terminal 21 of the decoder 2 via the latch circuit 4, and when an output signal is suddenly generated at the output terminal 2 of the decoder 2, this signal is held by the latch circuit 4. , is supplied as a switching signal terminal 3oK selection command signal of the selector 3. Further, when the selection command signal is not supplied to the switching signal line 3C, the selector 3 sends out an address signal representing the second address supplied to the input terminal group 3Al to 3/4 to the output terminals 301 to 304. , when a signal is supplied to the switching signal terminal 3C, the input terminal group 3
B1-184 Sends the address signal supplied from the CPU 1 to the output terminals 301-3D4.

ROM5> and RAM6 are address buses ABO.
~Input Bl 5 Kli is connected, and CP is in ROM5.
An instruction for U1 to send an address signal representing the first address and a decoder selection signal, and an instruction to be executed by cpσ1 are written.

The operation of the data processing apparatus according to the present invention configured as described above is as follows. When a reset signal is supplied from an external device (not shown), this reset signal is supplied to the buffer T, and is supplied to the reset input terminal R of the latch circuit 4 via an integrating circuit including a resistor 8 and a capacitor 9.
Since the reset signal is also supplied to the reset input terminal R of the CPU 1, the CPU performs a reset operation. And CPU1 was reset to just over 1m.

An address representing a zero address on address buses ABO to A1115.

sends a response signal.

Of the address signals representing this zero address, BQ to A87
The signal sent to is supplied to the decoder 2, but since this address signal is not rounded off as an address signal representing the first address, the decoder 2 does not generate an output signal, and accordingly, the latch circuit 4 also outputs a selection command. Does not generate a signal.

On the other hand, one of the address signals 112 to 8 B1504 representing the letter zero address is sent to the address bus ABO-A115.
The bit portion is supplied to selector 30 input terminals 3B1-384. However, since the selection command signal is not generated in the latch circuit 4 and the switching signal 3eK% signal of the selector 3 is not supplied, the output terminals 3Dl to 3D of the selector 3
4K is the address signal supplied from the CPU to the input terminals 381 to 3B4, and is not sent to the input terminal 3A.
Atto representing the second address supplied to 1 to 3 people 4
A response signal is sent.

As a result, the signals sent to the address buses ABO to 815 are the address signals corresponding to the zero address from address buses ABO to ABII, and the signals sent from the input terminals 3 to 3 of the selector 3 to 815 from AB12 to 815. The address signal representing the second address supplied to the ROM 5 and the address signal of both Table 1 are supplied to the ROM 5 via the address bus ABO~av15t-.
supplied to

As described above, the ROM 5 has written therein instructions for the CPUI to send an address signal representing the first address and a decoder selection signal, and instructions to be executed by the C'PU 1. Therefore, if the address specified by the address signal supplied to ROM 5 is the address of the instruction written in ROM 5, the data corresponding to the instruction written in ROM 5 will be sent to the data bus. be done. And C
PU1 takes in this data, decodes it, and sends it to the output terminal l.
A decoder selection signal is sent from 0RQ, and an atto indicating the first address determined for the decoder 2 is sent.
sends a response signal. As a result, decoder 2 detects the supplied address signal and generates an output signal at output terminal 2aK. This output signal is latched by the latch circuit 4 and supplied to the switching signal terminal 3C of the selector 3 as a selection command signal. As a result, the selector 3 output terminal 3D1
~3D4, which was sending out signals from input terminals 3M1 to 3A4, now sends out signals from input terminals 3B1 to 314. As a result.

All signals sent from the output terminal ADH of the CPUI are supplied to the address bus ABO-input 815. Then, the execution of subsequent instructions is done in ROM! Since the processing is performed according to the information written in $, the CPU 1 can be operated even if the RAM area is allocated to an area starting from address zero.

In addition, in the actual example, the input terminals 3ml to 3 of the selector 3
Although the signal supplied to A4 is fixed, if this is changed by a switch or the like, the signal output from the selector 3 after the reset condition can be changed arbitrarily. In the Makumi Ume example, only some bits of the address bus input 8G-A115 were switched by the selector, but all bits may be switched.

As explained above, the data processing device according to the present invention selects the address 0 representing the second address from the selector after the reset state is deafened.
The original W, which is supplied with both a part of the address signal representing the zero address sent from the CPTJ and an address signal representing the second address marked with #, is %.
The CPU sends a command to the data bus to send an address signal representing the fourth address, and the output signal of the decoder that detects the address signal representing the first address causes the selector to send the address signal representing the second address. °CPU from response signal
Since the switching is performed so that the address signal that is normally output is output, even if the RAM area is allocated starting from address zero, the CPU after being reset can be operated by a simple circuit.

[Brief explanation of the drawing]

The figure is a block diagram showing one practical example of the present invention. 1.@φ microcomputer (CPTJ), 2.
...Decoder, 3.Φ..Selector, 4..Fist latch circuit, 5..e.Read only memory (ROM),
6...-Random access memory (M to R). Patent applicant: ShinNippon Electric Co., Ltd. agent Masaki Yamakawa (and one other person)

Claims (1)

[Claims] In a data processing device equipped with a random access memory that writes and reads data supplied from a data bus to an address indicated by an address signal output from a central processing unit to an address bus, the zero address is set to zero at the time of reset. a central processing unit that sends out an address signal representing a predetermined first address; a decoder that generates an output signal when an address signal representing a predetermined first address is supplied; a latch circuit that generates a selection command signal; a first input terminal group to which an address signal sent from an address signal output terminal of the central processing unit is input;
and a second input terminal group into which an address signal representing a predetermined second address different from the address of A selector is sent to the address bus, and when the central processing unit is sending out an address signal representing a zero address and the selector is outputting an address signal representing a second address, the central processing unit is A data processing device comprising a read-only memory that sends data to a data bus that instructs to send an address signal representing an address.