JPS6214856B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a bit processing device for a microcomputer, and more particularly to a bit processing device that greatly expands the range of bit-processed data. Generally, a microcomputer has a first bus line 1 and a second bus line 2, as shown in FIG.
and an arithmetic processing unit (hereinafter referred to as ALU) 3 for processing the data sent thereto. An input/output terminal 4 and a RAM 5 for storing data are connected to the first bus line 1, and data applied to the input/output terminal 4 or data stored in the RAM 5 is sent to the second bus line 2. A register 7 that specifies the address of the ROM 6 and RAM 5 that stores the program or the input/output terminal 4
are connected via decoders 8 and 9 and switching circuits 10 and 11. That is, if it is not a bit processing instruction, the data in the ROM 6 or the contents of the register 7 is sent as is to the second bus line 2, and in the case of a bit processing instruction, the control signal M ₁ or M ₂ is sent to the second bus line 2.
The data in the ROM 6 or the data decoded from the contents of the register 7 are sent out, and the decoded data and the data on the first bus line 1 are subjected to predetermined processing by the ALU 3, and bit processing is performed. Ru. Therefore, in the above method, it is the decoder 8 that specifies the predetermined bits of the data to be bit processed.
This can only be done using the data in the register 7 and ROM 6 provided with 9 bits, which narrows the range of bit processing and requires a plurality of decoders 8, 9 and switching circuits 10, 11, resulting in an increase in the number of elements. The present invention has been made in view of the above-mentioned drawbacks, and provides a bit processing device for a microcomputer that eliminates the conventional drawbacks by providing a switching circuit and a decoder in front of one input of an ALU. It is. The present invention will be described in detail below with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention, in which 12 is a first bus line consisting of 4 bits;
13 is a second bus line consisting of 4 bits, 14
is an ALU, 15 is a decoder, and 16 is a switching circuit. For example, the first bus line 12 has an input/output terminal 1.
7 and a RAM 18 for storing data are connected, and data applied to the input/output terminal 17 or data stored in the RAM 18 is sent out, and these data are applied to one input of the ALU 14. For example, the second bus line 13 has
A register 19 for addressing the RAM 18 or a ROM 20 storing a program is connected, and the contents of the register 19 or the instruction code of the ROM 20 are sent out. Predetermined 2 of the 4 bits of the second bus line 13
The bits, for example the lower two bits, are applied to the decoder 15, which converts them into 4 bits and outputs them to the switching circuit 16. Furthermore, all four bits of the second bus line 13 are applied to the switching circuit 16, and the switching circuit 16 is configured to switch to the second bus line 13 according to the switching control signal M.
data on bus line 13 or decoder 15
is applied to the other input of the ALU 14. ALU14 is a 2-bit calculation selection signal
Depending on the contents of C ₁ and C ₂ , addition (ADD), logical product (AND), logical sum (OR), exclusive logical sum (EX-
OR) is selected, processes the 4-bit data applied to each input, and outputs it from ALUOUT.
In addition, the ALU 14 to which the output of the switching circuit 16 is applied
An inverting/non-inverting circuit 21 is provided at the input of the switching circuit 16, and inverts or non-inverts the 4-bit data from the switching circuit 16 depending on the control signal C/〒. In the case of normal arithmetic processing, for example, in the case of an arithmetic instruction such as addition, data sent to the first bus line 12 is taken in from one input of the ALU 14,
The data sent to the second bus line 13 is transferred from the switching circuit 16 to the ALU 14 according to the switching control signal M.
The ALU 14 receives the signals C ₁ ,
Perform the process determined by C ₂ , for example addition process,
Output the result from ALUOUT. In the case of bit processing instructions, for example, there are processing instructions such as setting a predetermined bit, inverting a reset, and testing.
The bit data is sent out to the second bus line 1.
3, data specifying a predetermined bit of the 4-bit data on the first bus line 12 is sent. That is, a predetermined bit is designated by the lower two bits of the second bus line 13. Assuming that the four bits of the first bus line 12 are the 0th, 1st, 2nd, and 3rd bits from the lowest order, the contents of the lower two bits of the second bus line 13 that specify these bits are as shown in Table 1. The content of the upper 2 bits is either 0 or 1.

[Table] That's fine. The lower 2 bits are applied to the decoder 15 and converted into 4-bit data in which predetermined bits are set to 1, as shown in Table 1. Alternatively, the output of the decoder 15 may be data in which only predetermined bits are 0. On the other hand, a switching control signal M is applied to the switching circuit 16 according to a bit processing command, and the switching circuit 16 applies the 4-bit output of the decoder 15 to the ALU 14. When the control signal C/〒 generated by the bit processing command is 0, the inverting/non-inverting circuit 21 of the ALU 14 non-inverts the output of the decoder 15, that is, keeps it as it is.
It is sent to ALU14, and when it is 1, it is inverted and sent. Also, the operation selection signal generated by the bit processing instruction.
C ₁ and C ₂ are assigned to ALU14 as shown in Table 2 depending on their contents.
determine the behavior of Therefore, the first

[Table] By subjecting the data on the bus line 12 and the output of the decoder 15 to predetermined processing in the ALU 14, predetermined bit processing is performed. Next, I will give a concrete explanation. (A) When setting the 0th bit when the data on the first bus line 12 is 0110, a set instruction is used as the bit processing instruction. The data specifying 0, that is, ××00, is sent to the second bus line 13, and the output of the decoder 15 is
Set to 0001. In the set command, the control signal C/〒 is 0 and does not perform inversion, and the operation selection signal
C ₁ and C ₂ are 1, 1 and cause the ALU 14 to perform an OR operation. Therefore, the data on the first bus line 12
By ORing each bit of 0110 with each bit of output 0001 of the decoder 15, the result becomes 0111, and only the bit specified by the data on the second bus line 13 is set to 1. (B) When resetting the first bit when the data on the first bus line 12 is 0110, a reset command is used as the bit processing command. The data on the second bus line 13 sends data specifying the first bit, ie, ××01, and the output of the decoder 15 is
0010. In the reset command, the control signal C/〒 is inverted when it is 1, and the operation selection signal
C ₁ and C ₂ are 1 and 0, causing the ALU 14 to perform an AND operation. Therefore, the data on the first bus line 12
Inversion of each bit of 0110 and the output of decoder 15
Depending on the AND with each bit of 1101, the result is 0100
Therefore, only the specified bits are reset. (C) When the data on the first bus line 12 is 0110,
When inverting the second bit, an inversion instruction is used as the bit processing instruction. Second bus line 13
Data xx10 specifying the second bit is sent, and the output of the decoder 15 becomes 0100. In the inversion command, the control signal C/〒 is 0 for non-inversion operation, and the operation selection signals C ₁ and C ₂ are 0 and 1 for EX-OR
The ALU 14 is made to perform the operation. Therefore, depending on the EX-OR of each bit of the data 0110 of the first bus line 12 and the output 0100 of the decoder 15, the result is
0010, and only the specified bit is inverted. (D) When the data on the first bus line 12 is 0110,
When testing whether the third bit is 0 or 1,
Bit processing instructions use test instructions. Data ××11 specifying the third bit is sent to the second bus line 13, and the output of the decoder 15 is
It becomes 1000. In the test command, the control signal C/〒 is 1 to cause an inversion operation, and the calculation signals C ₁ and C ₂ are 1, 1 to cause the ALU 14 to perform an OR operation.
Therefore, each bit of data 0110 on the first bus line 12 and each bit of 1000 output from the decoder 15 are
1000 is obtained by AND, and the test can be performed using the output of ALUZ. That is, the NOR output of each bit of ALUOUT is output as ALUZ, and when the designated bit is 0, 1 is output, and when it is 1, 0 is output. The output of this ALUZ is used for processing after the test instruction is executed, such as jump. As described above, according to the present invention, it is possible to specify a predetermined bit of data on the first bus line to be bit-processed based on a predetermined two bits of all data sent to the second bus line, and further, The number of elements constituting the decoder and switching circuit is also reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 12...First bus line, 13...Second bus line, 14...ALU, 15...Decoder,
16...Switching circuit, 17...Input/output terminal, 18...
...RAM, 19...Register, 20...ROM, 2
1...Inverting non-inverting circuit.

Claims (1)

[Scope of Claims] 1. A microcomputer equipped with first and second bus lines and an arithmetic processing unit to which data sent to the first and second bus lines is applied and performs predetermined processing. A decoder for decoding predetermined 2 bits of the second bus line into 4 bits, and a switching circuit for switching and outputting the output of the decoder and the data on the second bus line to the arithmetic processing device, A bit processing device for a microcomputer, characterized in that one bit specified by two predetermined bits of the second bus line, out of the data on the first bus line, is operated in a predetermined process of the arithmetic processing device. 2. A bit processing device for a microcomputer according to claim 1, wherein the switching circuit switches the output of the decoder using a switching control signal generated in response to a predetermined command. 3. According to claim 1, the arithmetic processing device is characterized in that addition, OR, and exclusive OR are selected and executed in response to an operation selection signal generated in response to a predetermined command. A bit processing device for a microcomputer. 4. The microprocessor according to claim 1, wherein the arithmetic processing device has a function of inverting or non-inverting the output of the decoder depending on an inversion control signal generated in response to a predetermined instruction. A computer's bit processing unit.