JPH0121383Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to an I/O expansion circuit that allows the number of I/O ports to be expanded as necessary.

(Prior art) In recent years, microcomputers have come into widespread use due to the advancement and development of semiconductor technology, and it is now possible to replace most parts of electronic circuits that were traditionally constructed using hard logic with microcomputers. I'm getting used to it. On the other hand, microcomputers themselves have become more sophisticated, from initially being about 4 bits to 16 and 32 bits, and on the other hand, 1-bit microcomputers and bit slice type ones have been developed, making them more versatile. I am perfecting my skills. In the field of electron microscopes as well, 1-bit microcomputers have recently come to be incorporated and used in, for example, exhaust system control circuits.

By the way, in electron microscopes and the like, the number of input/output points to be controlled differs significantly between different models. Therefore, if the circuit is designed with the maximum number of I/Os in mind, the cost may increase depending on the model. Therefore, a certain limit must be placed on the number of I/O ports. For this reason, although conventional hard logic has been replaced with a microcomputer and it has become possible to change the sequence flexibly, some models lack the number of I/O ports, so separate printed boards have to be designed. It was being produced.

(Purpose of the invention) The present invention was made in view of the above points, and its purpose is to realize an I/O expansion circuit that can easily cope with an increase in the number of I/Os. .

(Structure of the invention) The present invention that achieves the above object is equipped with a plurality of I/O ports and a subtraction circuit that inputs the high-order bit part of the address bus and performs a predetermined subtraction process, and transmits the information to the outside. A basic unit that outputs an address with a number of bits one bit less than the internal address, a subtraction circuit that receives the address signal output from the basic unit, inputs its upper bit part, and performs a predetermined subtraction process, and the upper bit part is all "O". ``, and a decoder that inputs the lower bit part of the address signal.The output of the detection circuit activates the decoder, and the output of the subtraction circuit and the output of the subtraction circuit are provided. The device is characterized in that it is constructed by an extension unit configured to synthesize the lower bit portions that do not exist and output the result to the outside as an address.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the structural concept of the present invention.
As shown in the figure, the present invention consists of a basic unit K and expansion units K ₁ to _{K o} (n is an integer). The basic unit K is equipped with a plurality of I/O ports, which must be provided in any case.
That is, if all the necessary I/Os can be connected using the number of I/O ports provided in the basic unit K, there is no need to provide an expansion unit. On the other hand, if the basic unit K alone does not have enough I/O ports,
As shown in the figure, expansion units K ₁ -K _o are sequentially connected via cables CA ₁ -CA _o to realize the required number of I/O ports. here,
Each expansion unit K ₁ to _{K o} needs to have an individual address, but it is inconvenient to provide an address setting switch for each expansion unit and set an address for each expansion unit each time.
This also leads to increased costs. Therefore, in the present invention, an address decoding circuit is provided in each of the expansion units _K1 to _K0 to identify each expansion unit.

FIG. 2 is an electrical circuit diagram showing a specific configuration of the present invention. Components that are the same as those in FIG. 1 are designated by the same numbers. The figure shows 8 addresses from A ₀ to A ₇ .
The case of bit is shown. The figure shows a case where the basic unit K and the first stage expansion unit _K1 are connected. In the figure, CN ₀ is the address output connector on the basic unit K side, and CN ₁ is the input connector of the expansion unit K ₁ that receives the address signal output from the address output connector CN ₀ via the cable CA ₁ . ₁ ' is an output connector for outputting the address signal synthesized within the expansion unit _K1 to the outside. The basic unit K, the expansion unit _K1 , and the expansion units can be easily expanded by connecting the output connector and input connector of each unit with a cable.

1 is a decoder that receives the upper 4 bits of the address, and 2 is the upper 4 bits of the address A ₄ to _{A 7}
This is a subtraction circuit that receives the value at the A input and a predetermined value at the B input, calculates A-B, and outputs the result. The subtraction circuit 2
3-bit data A ₄ ′, A ₅ ′,
A ₆ ′ is output. Then, this 3-bit data is the upper bit, and the lower 4 bits of the address that do not pass through the subtraction circuit 2, _A0 to _A3 , are the lower bits.A total of 7 bits are output as a new address signal to the outside from the output connector _CN0 . Ru. Applicable connector CN ₀
In addition, data write (DATAWRITE) is used to give data write commands to each unit.
A signal is output. Furthermore, the output of decoder 1 and the lower 4 bits of the address _A0 to _A3 are the basic unit K.
It is used as an address selection signal for I/O handled within the internal memory.

11 is connected to the basic unit K via cable CA ₁ .
The top 3 of the 7 bits of the address sent from
A subtraction circuit that receives bits _A4 ' to _A6 ' at its A input and a predetermined value at its B input, calculates A-B, and outputs the result.
2 is a decoder that receives the lower address bits A ₀ to A ₃ , and B is a detection circuit that detects whether the upper 3 address bits A ₄ ' to _{A 6} ' are all "0".
The detection circuit 13 detects the upper three bits of the address _A4 '~
When A ₆ ' is all "0", for example, "1" is output. This signal then enters the decoder 12 as a chip select signal. That is, the decoder 12 is configured to become active when the upper three bits of the address are all "0".

Further, the data write signal sent from the basic unit K is separated from the bus and used within the expansion unit _K1 . C output C ₀ of subtraction circuit 11
~ _C2 and the lower 4 bits of the address _A0 ~ _A3 are combined,
7-bit new address signals A ₀ , A ₁ , A ₂ ,
A ₃ ″, A ₄ ″, A ₅ ″, A ₆ ″ output connector
It is output externally from CN ₁ ′. A data write signal is also output from the connector CN ₁ '. Although the figure shows only one extension unit _K1 , as shown in FIG. 1, as many extension units as necessary can be connected.
To explain the operation of a circuit configured in this way,
It is as follows.

First, the operation of the basic unit K section will be explained. The basic unit K has a predetermined number of I/O ports, and selects a predetermined I/O with an address selection signal. Since the address is 8 bits from _A0 to _A7 , addresses from 0 to 127 are selected as the I/O selection signal within the basic unit K. Among these addresses, the upper 4 bits _A4 to _A7 are passed through the subtraction circuit 2 to perform predetermined subtraction processing. That is, the upper 4 bits A ₄ to _{A 7}
enters the A input of the subtraction circuit 2, while its B input contains a predetermined value, and the subtraction circuit 2 inputs (A-
B) Performs the subtraction and outputs the result from the C output. Now, if the B input value is 8, the C output will be 3 bits, _C0 to _C2 and _A4 ' to _A6 ', as shown in the figure. The basic unit K generates new 7 bits A ₀ , A ₁ , A ₂ , A ₃ , A 4 _′ , A ₅ ′, A ₆ ′ by combining the upper 3 bits and the lower 4 address bits A _{0 to} A 3 . Output externally as an address. As previously mentioned,
The basic unit K uses addresses from 0 to 127 as an I/O selection signal, and can specify addresses from 128 to 255 with 7 bits output as an external address signal.

It is assumed that each expansion unit has 16 I/O ports. These I/O ports use the lower 4 bits of the 7 bits of the address A ₀ ~
Decode and specify A ₃ . In the expansion unit _K1 , a decoder 12 performs this function. however,
The decoder 12 does not perform the decoding function unconditionally, but only when a chip select signal is outputted to the decoder 12 from the detection circuit 13.
That is, the upper 3 bits of the 7 bits of the address
Only when A ₄ ′ to A ₆ ′ are all “O”.
A state in which all of A ₄ ' to _{A 6} ' are set to "O" means that only the expansion unit _K1 is selected. In this way, the upper three bits of the address are used to automatically select units for units that are added one after another.

The upper three bits of the expansion unit _K1 are input to the A input of the subtraction circuit 11, and are subjected to a predetermined subtraction process (A-B) with the value set at the B input. Since "1" is set in the B input, "1" is subtracted from the value set by the upper 3 bits to obtain the C value.
The output is output as 3-bit data _A4 '' to _A6 ''. The upper 3 bits with this "1" subtracted and the lower 4 address bits _A0 to _A3 are combined and output to the output connector as a new 7-bit address signal.
It is output externally from CN ₁ ′. The same applies to the data write signal. That is, for the next stage,
It is configured to subtract 1 from the upper 3 bits of the address from the previous stage and send the result. According to such a configuration, eight expansion units can be connected using the circuit shown in the figure.

Thus, according to the present invention, the basic unit K
When viewed from above, the first stage expansion unit _K1 is 128~
It can be assumed that it occupies the address space at address 143, and the next stage expansion unit (not shown) occupies the address space at addresses 144-159. In this way, 16 addresses can be assigned to each expansion unit, and the addresses can be automatically set sequentially using the same expansion unit. Since the address is sent to the next stage by subtracting 1 from the upper 3 bits as described above, a state in which all the upper 3 bits are "O" does not occur in two or more expansion units. Therefore, only one expansion unit is automatically selected at any time. In the above description, the case where the basic address is 8 bits is taken as an example, but it is not limited to this and may be any number of bits. Furthermore, the microcomputer used is not limited to a 1-bit microcomputer, but may be any number of bits, such as 8-bit.

(Effects of the invention) As explained in detail above, according to the invention, a division is made between the basic unit and the expansion unit, and the expansion unit is connected to the next stage, and the expansion unit is connected to the next stage. By subtracting a predetermined number from the high-order bit part of the new address for the expansion unit to be added, the required number of expansion units with the same circuit configuration can be connected as needed. Therefore, it is possible to easily cope with an increase in the number of I/Os.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the structural concept of the present invention, and FIG. 2 is an electric circuit diagram showing the specific structure of the present invention. 1, 12...decoder, 2, 11...subtraction circuit, 13...detection circuit, K...basic unit,
_K1 to K _o ...Extension unit, _CA1 to CA _o ...Cable, _CN0 , _CN1 , _CN1 '...Connector.

Claims (1)

[Scope of utility model registration request] It is equipped with multiple I/O ports and a subtraction circuit that inputs the high-order bit part of the address bus and performs a predetermined subtraction process.
A basic unit that outputs an address with a small number of bits, a subtraction circuit that receives the address signal output from the basic unit, inputs its high-order bit part, and performs a predetermined subtraction process, and a state in which all the high-order bits become "O". a detection circuit that detects the address signal, and a decoder that inputs the lower bit portion of the address signal, and activates the decoder with the output of the detection circuit, and detects the output of the subtraction circuit and the lower bit portion that does not pass through the subtraction circuit. An I/O expansion circuit configured with an expansion unit configured to synthesize and output externally as an address.