JPS593440Y2 - memory selection device - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to a memory selection device.

Conventionally, as an addressing method for information processing devices having memory sections such as ROM (read only memory) and RAM (random access memory), address data is divided into two groups, upper bits and lower bits, and multiple memories are used. A method of specifying a chip or a plurality of memory blocks within one chip is generally used.

According to this method, for example, in an information processing device composed of 16-bit address data, the upper 4 bits are assigned to memory chip (block) selection signals, and the lower 12 bits are assigned to each chip (block). By allocating to the address designation signal, 16 memory chips each having 94096 address values can be provided.

However, when the program data stored in the memory chip is required for program processing reasons, for example, when another program is processed by the same central processing unit, the address specified by the central processing unit is It was not possible to run different programs without changing the specification method or replacing the memory itself.

Therefore, in such a case, there are disadvantages in that the address data length becomes long or continuous processing cannot be executed.

Furthermore, it was not possible to address more memory than the memory capacity determined by the address length.

In other words, the memory area that can be specified by address data having a length of 12 bits has a memory capacity of 4096 addresses.
It was not possible to specify an address for more memory than that.

Therefore, in order to perform more complicated program processing that requires a large memory area, it is necessary to use a processing device that has an address length that can specify the memory capacity.

Furthermore, in a processing device with a long address length, when transferring address data in parallel, the central processing unit (CPU)
) and the memory, which increases the size of the device.Especially when the memory is constituted by a separate chip, the number of external terminals for address specification increases.

On the other hand, when address data is transferred serially using one address bus, the longer the address data, the longer the transfer time becomes, resulting in a significant drop in processing speed.

In this way, it is extremely difficult to increase the memory in an information processing device with a fixed address length, and changing the processing program involves the cumbersome task of having to replace the memory each time. .

An object of the present invention is to provide a memory selection device that can increase memory capacity without increasing address length.

The memory selection device of the present invention uses a switch to switch the memory block to be selected in response to a chip selection signal to which the upper bits of the address data are assigned in order to select a memory chip or a memory block. It is characterized by being used as a chip selection signal for.

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG.

In the figure, reference numeral 1 denotes a central processing unit having an arithmetic processing function, which has 16 address buses 5, 5' and 8 data buses 6. The upper 4 bits of the 16-bit address data 5' is used as a chip selection signal to the memory chip, and is decoded by the address decoder 2.
memory chips can be selected.

Reference numeral 3 designates a ROM to which a lower 12-bit address bus 5 and an 8-bit data bus 6 are connected, and is a memory that is selected via a chip selection signal terminal C3 when the upper address bit 5' is 0000.

Here, the other 15 output from address decoder 2
The memories selected by the actual chip selection signals are omitted.

On the other hand, ROM4 is a memory that stores new program codes required for program processing, and is a memory that should be externally attached to this information processing device.
Switch 7 is connected to the chip selection signal output terminal for selecting OM3.
connected via.

This switch 7 may be a manual changeover switch.

According to this configuration, the newly required memo J (RO
M4), the address data that should address this ROM4 can be set by simply switching switch 7.
The data may be the same as the data specifying OM3.

Furthermore, when addressing different memory blocks, it is possible to specify the memory using continuous address data without changing the address value.

In this way, there is no need to increase the address length for large-capacity memory areas, and there is no need to replace ROM3 with ROM4, and the same address can be used to specify addresses for other memory blocks. Different program processes can be executed, and additional memory can be easily expanded.

By using the memory selection device of the present invention, it is possible to construct a particularly versatile information processing system, and by adding new memory, it is possible to execute more advanced processing than more complex processing.

Note that the ROMs 3 and 4 of this embodiment may be memories formed in the same chip together with the CPU 1, and these may be
It may be used in place of M.

Furthermore, it is clear that by using a multi-pole, multi-contact switch other than a two-pole, two-contact switch as the switch 7, it is possible to add more memory blocks. , a switching gate circuit that is switched by a control signal from the CPU 1 may be used.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an information processing device including a memory selection device showing one embodiment of the present invention. 1...CPU, 2...Address decoder, 3,4...ROM, 5,5'...
Address bus, 6... Data bus, 7...
··switch.

Claims (1)

[Scope of utility model registration request] selection signal generating means having a plurality of output terminals for outputting a plurality of selection signals for individually selecting a plurality of memory blocks by decoding a part of the address information; and at least one of the plurality of output terminals. The switch comprises a manual switch means, one of which is connected to an output terminal and the other of which has a plurality of terminals, and a plurality of memory blocks connected correspondingly to the other plurality of terminals of the switch means. The device is characterized in that one terminal of the other plurality of terminals is connected to the one of the plurality of terminals of the other terminal to apply a selection signal to only one of the plurality of memory blocks by operating the means. memory selection device.