JPS6072450A - Line control system - Google Patents

Abstract

PURPOSE:To attain ease of extending job of a unit by connecting a unit mounting section and a selection with a connecting line having the maximum number of storage lines per unit and providing an address converting section between an address generating section and the selection section. CONSTITUTION:The selection section 13 and the unit mounting section are connected in advance by mXn of connecting lines S11-Smn, where (m) is the maximum mounting number of the units 14 and (n) is the maximum number of storage lines per unit, and the address generating section 12 is constituted to generate an address signal corresponding to the maximum number storage line (p). The address converting section 15 consists of memories or the like, the address signal is converted to designate a line individual section of the mounted units and its signal is supplied to the selection section 13. An address designating the line individual section is written in the said memory MEM. Thus, the connection between the selection section 13 and the individual section is performed by only mounting the units to the unit frame, the address signal is converted at the conversion section 15 by writing the address of the line individual section in the unit to the memory MEM, and the line individual section is designated without designating an idle connecting line.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line control system that can easily and economically deal with the addition of individual line units.

In line control equipment that has multiple individual line units, the individual line units are often added within the maximum number of lines that can be accommodated, and the equipment is usually installed in units equipped with multiple individual line units. It will be expanded by inserting it into. In this case, the number of accommodated lines often differs depending on the type of unit. Therefore, in the past, a method has been adopted in which terminal connections are made each time an extension is installed, or the equipment rack is connected in advance in accordance with the maximum number of lines that can be accommodated in the unit.

For example, as shown in FIG. 1, an address signal specifying the individual line section is generated from the address generation section 2 under the control of the signal processing section 1, and the address signal is decoded in the selection section 6. In the method of specifying the line-individual section, the selection section 6 is provided with terminals S, .about.sp for the maximum number of lines p that can actually be installed.

Connect to the terminals of units 41 to 4m to add more units. Each selector 6o'1I7j connects the child to the terminal of the unit. Unit 4. indicates the case where two individual line sections are installed, and the terminals L1 to L? and terminal S,
~ Becomes the connection point where the connection with Sf is made. This servant 6'
, even if the number of accommodated lines of the units is different, it is possible to connect up to the maximum number of accommodated lines P to the terminals 51 to sp of the selection section 6 without waste, and the address generation section 2 can be connected to the terminals S and -5p of the selection section 6. A configuration that generates an address signal that can specify the address will suffice.

However, since connection work is performed each time a unit is added, a terminal board is required, and there is a risk that erroneous connections may occur during manual connection. .

Also, as shown in Figure 2, the maximum number of units installed is m,
When the maximum number of lines that can be accommodated by a unit is n, the selection section 3 and the mounting section of the unit are connected in advance 1iJS□~s
In the conventional example in which the address generator 2 is configured to be able to generate an address signal capable of specifying addresses outside the range by connecting the units 41 to 4m with mn, no connection work is required when adding units 41 to 4m. , the number of connected lines is m for the maximum number of accommodated lines p
Since the relationship is p<(mX %), the address generation section 2 and the selection section 3 are configured to
The disadvantage is that additional configurations must be added to the required configuration. Furthermore, unit 4. ~4m are not necessarily equipped with individual line sections that are outside the maximum number of lines that can be accommodated, so when the connection lines S□□~smn are sequentially scanned by decoding the address signal, there are empty connection lines. In particular, it has the disadvantage of requiring additional processing time.

The present invention improves the conventional drawbacks as described above, and eliminates the need for connection work when adding units, and only requires processing for the maximum number of lines that can actually be installed. The purpose is to Examples will be described in detail below. .

FIG. 3 is a block diagram of an embodiment of the present invention, where 11 is a signal processing section, 12 is an address generation section, 13 is a combustion selection section, -
14, to 14m are units equipped with a plurality of line individual units, and 15 is an address translation unit. When the maximum number of units installed is m, and the maximum number of lines per unit is n,
The selection section 13 and the mounting section of the unit are connected in advance by II connection lines 511 to Smn, and the address generation section 12 is connected to the maximum number of lines that can be accommodated, which is determined by the □ processing capacity of the signal processing section 11, etc. The configuration is such that an address signal corresponding to p can be generated.

The address conversion unit 115 is configured with a memory, etc., and converts the address signal from the address generation unit 1'2 so that it can specify one line individual section of the mounted unit, and selects a converted address signal. This is added to Section 13.

FIG. 4 is an explanatory diagram of the address conversion section 15, and is an explanatory diagram of the address conversion section 15.
JIEM has an area for the maximum number of lines p, and an address designating one individual line is written in each area.

This address is set during initial setup or when adding units.
Items written by input operations from a keyboard, etc.lch
Ru.

Therefore, by simply mounting two units on the equipment rack, nine connections are made between the selection section 13 and the individual section.Next, by writing the address of the individual line section in the unit into the memory MEN of the address conversion section 15, The address signal from the address generating section 12 is converted by the address converting section 15, and it is possible to specify an individual line section without specifying an empty connection line.

For example, if units are sequentially mounted to add individual line sections, the addresses of the individual line sections mounted on the gourd unit will be sequentially written into the memory kfEM of the address conversion section 15, and the connection lines 511 to Even if the number of S and 1B is greater than the number of individual lines 91 of the mounted unit and there are empty connection lines, the address signal converted by the address conversion unit 15 specifies the empty connection line. This means that the extra scanning time shown in FIG. 2 is eliminated.

As explained above, the present invention is equipped with a plurality of individual line units. Unit 14. ~14m will be implemented. The mounting section and the selection section 13 for specifying the individual line section are connected by the connections IfiISU to S- for the maximum number of lines that can be accommodated per unit, and the address conversion section is connected between the address generation section 12 and the selection section 15. 15 is provided, and a memo IJ J of the address conversion section 15 is provided.
By including the address signal from the address generation section 12 in correspondence with the address of the individual line section of the mounted unit in fEH, it is possible to input the address signal from the address generation section 12 into the mounted unit. The circuit is converted into an address signal that specifies the individual line section, and this address signal is decoded by the selection section 16 to specify the individual line section.When adding units by mounting them, connections between the terminals are made. This is no longer necessary, and it is sufficient to simply write the address of the individual line section of the unit mounted in the memory of the address conversion section 15, which has the advantage that the workability of expansion becomes extremely easy.

In addition, the address generation section 12 only needs to be configured to generate an address signal corresponding to the maximum number of accommodated lines p, and there is no need to generate an extra address signal, resulting in an economical configuration and address conversion by the address conversion section 15. Since there is no need to specify an empty connection line, there is no need to waste line access.

Note that since the address conversion section 15 has a relatively simple configuration, it does not increase in size or cost, and does not impair the advantages of the present invention described above. Also, address conversion section 1
Since the contents of the memory MEJf in step 5 can be checked using a judgment processing mechanism such as the signal processing unit 11, the check can be performed before actually connecting the line to perform highly reliable line control. be able to.

[Brief explanation of drawings]

1 and 2 are explanatory block diagrams of the conventional example;
The figure is a block diagram of an embodiment of the present invention, and FIG. 4 is an explanatory diagram of an address translation section. 11 is a signal processing section, 12 is an address generation section, 16 is a selection section, 141 to 14m are units, 15 is an address conversion section, 511 to smn are connection lines, and HEM is a memory. Patent applicant: 2 people from outside Fujitsu Limited Representatives: Patent attorney: 1 person from outside the company

Claims (1)

[Claims] In a line control method in which a unit equipped with a plurality of individual line units is mounted, and an address signal from an address generation unit is decoded by a selection unit to specify the individual line unit, a mounting unit for mounting the unit and A plurality of connection lines with the maximum number of lines that can be accommodated by the unit are connected to the selection section, and an address conversion section is provided between the address generation section and the selection section. -*=Setting: 4 The address conversion section includes a memory for storing the address signal from the address generation section and the address of the individual line section of the mounted unit in correspondence, and the address conversion section A line control system characterized in that the address converter converts the address signal into an address signal that specifies a line individual section of a unit mounted on the unit, and the address signal is decoded by the selection section to specify the line individual section.