JPS6122820B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device for data processing;
In particular, the present invention relates to an integrated circuit device having a read-only memory (hereinafter referred to as ROM) for storing a program and an execution unit for reading the program and executing processing on the same chip.

The operation confirmation test (hereinafter referred to as "test") of an integrated circuit device that has an internal ROM for storing programs is
ROM code check tests and functional tests of the ROM code decoder section and execution unit are conducted separately. This is a large part of the testing process and is invariant in the hardware configuration.
a ROM code decoder section and an execution unit section;
Contains variable instruction codes based on user requirements
By testing the ROM pattern separately, the decoder section and the execution unit section can be tested and evaluated using the same test code for many ROM code-changed products, and the ROM code check only requires modifying part of the pattern. This is because it allows various functional confirmation tests to be performed. Therefore, the test processing can be simplified and its speed can be improved. Note that mounting the program storage ROM, execution unit section, and decoder section on the same integrated circuit chip means that one instruction code (instruction code) can be processed without being limited by the number of external terminals (pins) of the integrated circuit device. ) can have a large word length, and complex processing can be executed by reading one instruction, which has the advantage of increasing processing speed. In such an integrated circuit device, when testing the decoder section and execution unit section separately from the program storage ROM, the test instruction code is set in the instruction register through an external terminal.
This is decoded by a decoder to generate a control signal (micro-order) for the execution unit, and under this control the execution unit is caused to execute processing and the results are checked. Furthermore, regarding ROM testing, a method has been used in which a code check is performed by sequentially fetching stored instruction codes to the outside and inspecting them. However, since the instruction code in the ROM generally has a long word length, it has been necessary to read it externally using a large number of terminals. Therefore, since circuits and wiring for reading out instruction codes were provided for these many terminals, there was a drawback that the circuit pattern and wiring pattern became complicated.

The purpose of the present invention is to provide a simple circuit and wiring structure.
An object of the present invention is to provide an integrated circuit device capable of checking ROM instruction codes. Another object of the present invention is to provide an integrated circuit device that enables efficient functional testing.

Next, an embodiment of the present invention will be described with reference to the drawings.

Figure 1 explains a conventional example, in which a program storage ROM 1 mounted on the same chip and a micro-order group are created by decoding the instruction code output from this ROM and controlling the timing of the resulting control signal. an instruction decoder 2 that outputs 3, an execution unit section 4 that executes a process determined based on these microorders 3, a sequence control system 5 that specifies addresses of the ROM 1, and an external terminal 7, when testing an integrated circuit device. and a gate circuit 6 which is switched during a processing operation and controls the connection between the terminal 7 and the decoder 2, and between the terminal and the ROM 1. In normal processing operation, this integrated circuit device:
The instruction code output from the program storage ROM 1 based on the content of the address determined by the order control system 5 is decoded by the decoder 2,
Microorder group 3 is generated. The execution unit 4 is controlled by these micro-order groups 3, and predetermined processing is executed. These series of operations are executed continuously according to the program corresponding to the address by continuously changing the address. Next, when testing this integrated circuit, the program storage ROM 1 and the decoder 2 are separated by the gate circuit 6, and the contents of the program storage ROM 1 are read in parallel from the external terminal group 7 for the word length and checked externally. Similarly, a new instruction code is input to the decoder 2 from the external terminal group 7 and the execution unit 4 is evaluated. Therefore, the number of external terminals used for testing has increased, and the circuits and wiring for inputting and outputting instruction codes have become complicated. In this regard, referring to FIG. 2, in the same figure showing one embodiment of the present invention, the gate circuit 16 is connected to the program storage ROM section 10 and the decoder/encoder 1.
2, the micro order group 3 is read out after the instruction code is decoded and the timing is controlled.

As a result, the instruction code of the program storage ROM 10 is checked and the decoder and encoder 12
can be effectively tested at the same time as the function check. The instruction code is finally read out by addressing from the order control system 15, and a group of control signals for controlling the execution unit 14 is created in the decoder and encoder 12, and these are controlled in timing to be processed as a micro-order group 13. Since they are output sequentially, this micro order group 13
In order to take out the data to the outside, if there is a terminal for at least one bit, it is possible to control the timing and evaluate all the micro-order groups generated at different times. Therefore, since the number of external terminals 17 used is reduced, the circuit and wiring can be simplified accordingly. Also, by switching the gate circuit 16, the micro-order forming signal can be transmitted from the same terminal to the execution unit 14 in series or with a small number of bits.
This makes functional evaluation extremely easy.

Note that any switching means may be used to control the switching of the gate circuit 16, such as switching a manual switch from outside or switching processing inside the device using a program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional integrated circuit device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1, 11...ROM for program storage, 2, 1
2... Instruction decoder, 3, 13... Micro order group, 4, 14... Execution unit, 5, 15...
ROM sequence control system, 6, 16...external terminal,
7,17...gate circuit.

Claims (1)

[Claims] 1 means for reading out a control signal to an external terminal for an execution unit that decodes an instruction code stored in a program storage memory and executes a process based on the instruction code; and a means for inputting the control signal from the external terminal to execute the execution. 1. An integrated circuit device comprising: a means for supplying a chip to a chip on the same chip.