KR100287891B1 - Test Subroutine Processing Equipment and Processing Method - Google Patents

Abstract

The present invention is to provide a test subroutine processing apparatus and a method for implementing the test subroutine operation in a hardware manner so that the address of the source program does not need to be changed for each test operation. A program memory that stores a test point address generator that generates a flag, a flag signal generator that generates a flag signal, a test point determiner that determines whether the current operation is normal or a test operation, a command for executing a program, and a command for a test operation. A decoder for performing a program instruction decoding and a test instruction decoding for a test operation, outputting a current program address during a test operation, a stack memory unit for storing a current program address during a test operation, and a test Any one of a test subroutine designation unit for designating a test subroutine address of a program memory unit in operation, a program counter for incrementing a program address by one, and an output address of the program counter, stack memory unit, and test subroutine addressing unit; Select and print mux

Description

Test Subroutine Processing Equipment and Processing Method

The present invention relates to a processor, and in particular, when a test program is to be executed during a normal program, a test subroutine processing apparatus capable of performing a test subroutine without changing the address of a normal program through a hardware configuration, and It relates to a treatment method.

Hereinafter, a test subroutine processing method according to the prior art will be described with reference to the accompanying drawings.

First, the test subroutine processing method according to the prior art is implemented in software.

That is, when a test operation is required during a normal program operation, the test operation is performed in software using a branch or a call instruction.

FIG. 1A schematically illustrates a program memory for explaining a conventional test subroutine execution method, and illustrates a program memory in normal operation, and FIG. 1B illustrates a program memory in a test operation.

As shown in FIG. 1A, in a normal operation, an instruction for executing a program (INST1, INST2, ...) is stored in a program memory according to a sequential increase of a program address, and an area in which the instruction for performing the program is stored. After that, the test commands (TEST INST1, TEST INST2, ...) are stored, and finally the return command (RETURN) is stored to sequentially perform the operation according to the command.

In this case, when the first instruction INST1 is executed and the result is stored in a subroutine or a command related to a special test operation is to be used, the instruction INST2 on the original source program as shown in FIG. Stores the command (CALL TEST) to run the subroutine.

The instruction INST2 on the source program is stored at an address next to an address at which the instruction (Call Test) for the subroutine operation is stored.

As a result, during the test operation, the command execution step is performed in the order of INST1 → CALL TEST1 → TEST INST1 → RETURN → INST2 → INST3 → INST4 → CALL TEST → TEST INST2 → RETURN → INST5 → INST6.

However, the conventional test subroutine execution method has the following problems.

When the test program operation (CALL TEST) is performed, the original source program stored at the corresponding address must be stored at the next address, so the address is changed.

That is, when a subroutine operation is called to a specific program address for a test operation during a normal operation, it is cumbersome to resave the source program from the first address to the next address each time.

The present invention has been made to solve the above-mentioned problems of the prior art, and provides a test subroutine processing apparatus and processing method by implementing a test subroutine operation in a hardware manner, without having to change the address of a source program for each test operation. Its purpose is to.

1A is a diagram schematically showing a general program memory.

1B schematically illustrates a program memory during a test operation according to the prior art.

2 is a diagram schematically showing a program memory during a test operation according to the present invention.

3 is a block diagram of a test subroutine processing apparatus according to the present invention

4 is a flowchart for explaining a test subroutine processing method according to the present invention.

Explanation of symbols for main parts of the drawings

31: test point address generator 32: flag signal generator

33: test point discrimination unit 34: program memory

35: decoder unit 36: stack memory unit

37: test subroutine address generator 38: program counter

39: musbu

The test subroutine processing apparatus of the present invention for achieving the above object is a test point address generator for generating an address in which a test point in a program memory is located, a flag signal generator for generating a flag signal, whether it is normal operation or test operation. A test point determination unit for determining a control unit, a program memory unit for storing a command for performing a program and a command for a test operation, performing a command for performing a program and decoding a test command for a test operation, and performing a current program during a test operation. A decoder unit for outputting an address, a stack memory unit for storing a current program address during a test operation, a test subroutine designation unit for specifying a test subroutine address for a program memory unit in a test operation, and a program address incremented by one And a mux section for selecting and outputting any one of a program counter, a stack memory section, and an output address of the test subroutine address designation section, and the test subroutine processing method of the present invention includes a test subroutine. A step of specifying a program address and a flag signal to call, a step of determining whether it is in a normal operation state or a test operation state, and in the case of normal operation, instructions of a program memory corresponding to a program address output from a program counter Performing a test operation; storing a current program address in a stack memory; performing a test command of the program memory corresponding to a test subroutine address according to the test operation; and determining whether the test operation is completed. Completed by If consists of a step for invoking the program address stored in the stack memory, perform the corresponding control instruction in the program memory thereof.

Hereinafter, a test subroutine processing apparatus and a processing method of the present invention will be described with reference to the accompanying drawings.

First, FIG. 2 schematically shows a program memory according to a test subroutine processing apparatus and a processing method of the present invention. As shown in FIG. 1B, the first program address is not changed, as shown in FIG.

3 is a block diagram illustrating the test subroutine processing apparatus of the present invention.

As shown in FIG. 3, the test point address generator 31 generating the test point address, the flag signal generator 32 generating the flag signal, and the current program address are compared with the test point address. A test point determining unit 33 for determining whether the flag signal is active or not, a program memory unit 34 storing instructions for executing a program and instructions for a test operation, and performing a program A decoder unit 35 for performing command instruction decoding and a test instruction decoding for a test operation, a stack memory unit 36 storing a current program address output from the decoder unit 35 during a test operation, and a test operation A test subroutine designation unit 37 for specifying a test subroutine address of the program memory unit 34, and In operation, any one of a program counter 38 for incrementing the current program address by one, an output address of the program counter 38, the stack memory unit 36, and the test subroutine address designation unit 37 is selected. It is comprised including the mux part 39 which outputs.

Here, the decoder unit 35 performs a test operation by decoding a test command of the program memory unit 34 corresponding to the address designated by the test subroutine address storage 37 during a test operation.

The operation of the test subroutine processing apparatus will be described in more detail as follows.

First, in the normal operation, the command of the program memory unit 34 is executed according to the program address designated by the program address counter 38.

At this time, the test point determination unit 33 determines whether the current program address and the user defined test point address match each other and whether the flag signal output from the flag signal generator 32 is active or non-active. When the addresses coincide with each other and the flag signal is active, it is regarded as a test operation.

At this time, execution of the program which has been performed so far is stopped and the current program address is stored in the stack memory unit 36.

Thereafter, the test subroutine address designation unit 37 outputs a test subroutine address in the program memory section 34 for performing a test operation.

Accordingly, the decoder 35 decodes a test command corresponding to the address specified by the test subroutine address designator 37 to perform a test operation.

Subsequently, when a return command is input, it is determined that the test operation is completed and the program address stored in the stack memory unit 36 is output.

Therefore, the instruction corresponding to the program address output from the stack memory unit 36 is performed.

This test subroutine processing method will be described using the flowchart shown in FIG.

First, a program address to call the test subroutine is designated (S401), and then the state of the flag signal is designated as active or non-active (S402).

Thereafter, after comparing the specified test point address with the current program address (S403), it is determined whether the specified test point address and the program address match each other (S404). S405).

If the test point address and the program address do not coincide with each other, the program address is incremented one by one (S406) to continuously compare the test point address with the current program address.

If the flag signal is not active, the test subroutine operation is not performed even if the program address and the test point address coincide with each other.

In addition, if the test point address and the program address do not match, the operation is recognized as normal operation and a command of a program memory corresponding to the program address is performed (S408).

On the other hand, if the program address and the test point address coincide with each other and the flag signal is active, normal program execution is paused, and the current program address is stored in the stack memory unit (S409).

The test subroutine address designation unit designates an address (S410) and performs a test command of a program memory corresponding to the designated address (S411).

Thereafter, it is determined whether a RETURN command is entered (S412). If the return command is input, the test operation is completed, and a program address stored in the stack memory unit is read (S413).

In operation S408, an instruction of a program memory corresponding to the program address is performed.

As described above, the test subroutine processing apparatus and processing method of the present invention have the following effects.

If the user wants to perform the test subroutine at the desired program address, the test subroutine can be performed without changing the original program address.

Claims (6)

A test point address generator for generating an address where a test point in the program memory is located; A flag signal generator for generating a flag signal, A test point determination unit for determining whether the current operation is normal or the test operation; A program memory unit for storing instructions for executing a program and instructions for a test operation; A decoder for performing a program instruction and a test instruction decoding for a test operation, and outputting a current program address during a test operation; A stack memory unit for storing a current program address during a test operation; A test subroutine designation unit for specifying a test subroutine address of the program memory unit during a test operation; A program counter that increments the program address by one, And a mux part for selecting and outputting any one of an output address of the program counter, the stack memory part, and the test subroutine address designation part. The test subroutine processing apparatus of claim 1, wherein the test point discrimination unit compares a current program address with a test point address to determine whether the test point is identical, and determines whether the flag signal is active. The apparatus of claim 1, wherein the mux unit outputs a program address output from the program counter during normal operation, an address output from the test subroutine address designation unit during a test operation, and the stack when the test operation is completed. And a test subroutine processing apparatus for outputting an address stored in a memory unit. The test subroutine process according to claim 1, wherein the test point determination unit determines a test operation only when an address output from the test point address generator and a current program address match and the flag signal is active. Device. Specifying a program address and a flag signal to call a test subroutine, Determining whether the operation state is normal or test; Performing a command of a program memory corresponding to a program address output from a program counter in a normal operation, and storing a current program address in a stack memory during a test operation; Performing a test instruction of the program memory corresponding to a test subroutine address according to a test operation; Determining whether a test operation is completed, and if the test operation is completed, reading out a program address stored in the stack memory and executing an instruction of a program memory corresponding to the test subroutine. The method of claim 5, wherein the determining of the normal operation time and the test operation time is performed by comparing the test point address with the current program address, and determining the test operation when the flag signal is active. Test subroutine processing method.