JPH0520036A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To provide the digital signal processing circuit of simple configuration which can perform plural kind of processes. CONSTITUTION:A program counter 2 is equipped internally with a 2nd ROM stored with many operation menus consisting of pairs of the head addresses and execution modes of plural main programs stored in a 1st ROM 4. When an address of the 2nd ROM is specified from outside, the operation menu stored in the address is read out of the 2nd ROM, the execution mode in the operation menu is decoded by a decoder to generates the address of the 1st ROM 4 according to the head address and the decoding result of the decoder, and the instruction stored in this address is read out of the 1st ROM 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit which stores a program in a ROM and executes the program in the order instructed by a program counter.

[0002]

2. Description of the Related Art Conventionally, digital signal processing circuits have been used in various fields such as voice information processing.
Only one main program is stored in the OM. Therefore, it is necessary to prepare many kinds of digital signal processing circuits in order to execute many different processes.

[0003]

However, in the digital signal processing circuit as described above, the cost is increased and it is against the space saving. In order to solve this, one main program can perform a large number of processes, for example, by inputting an on / off signal from the outside and determining whether the signal is on or off in the main program. Then, it may be possible to branch to an address in which a program for performing different processing is stored depending on whether the signal is on or off. However, if this method is adopted, the main program becomes complicated, and it becomes necessary to input a signal for program branching from the outside, which also results in a complicated configuration.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a digital signal processing circuit capable of executing a plurality of types of processing with a simple configuration.

[0005]

A digital signal processing circuit of the present invention for achieving the above object comprises a first storage means in which a program is stored and a program for sequentially designating addresses of the first storage means. In a digital signal processing circuit including a counter, the first storage means includes
A second memory for storing a plurality of main programs, wherein the program counter comprises a set of main program execution modes stored in the first storage means and a plurality of operation menus of the program counter. And a desired operation menu is designated from the outside, thereby executing the desired main program among the plurality of main programs stored in the first storage means in the desired operation mode. It is characterized by being configured as described above. Here, the above-mentioned "operation mode" refers to a mode in which, for example, an address designated when executing a program is incremented by +1 or +2.

[0006]

According to the digital signal processing circuit of the present invention, a plurality of main programs are stored in the first storage means and the second storage means is provided in the program counter according to the above configuration. In the means, a plurality of operation menus each including a start address of each main program and an execution mode of each main program are stored, and an operation menu corresponding to a desired process is externally selected from the plurality of operation menus. Designate and execute a desired main program according to the designated operation menu.
As a result, one digital signal processing circuit can perform a plurality of types of processing, and each main program is simplified compared to the case where a plurality of processings are performed by various branches in the main program. The number of bugs is reduced, and it is not necessary to input a signal for determining a branch from the outside, so that the digital signal processing circuit has a simple structure.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing an example of a digital signal processing circuit according to the present invention. The digital signal processing circuit of this embodiment includes a program counter 2, a first ROM 4 in which a combination of operation instructions is programmed and stored, and a sequencer / decoder for sequentially decoding the instructions stored in the first ROM 4. 6 and RAM8
And a RAM in response to an instruction from the sequencer / decoder 6
The address arithmetic unit 10 for designating the address 8; the multiplier 12; the arithmetic processing unit 14; the accumulator 16; the bus line 18; and the I / O interface 20.

The address of the program stored in the first ROM 4 is sequentially designated by the program counter 2, the instruction stored at this designated address is read by the sequencer / decoder 6, and this instruction is decoded and Instructions are issued to each section according to the instruction. Further, in response to this instruction, the address of the RAM 8 is instructed in the address calculation unit 10, and the RAM 8 is accessed. Further, if necessary, the data in the RAM 8 is input to the multiplier 12 to perform a multiplication operation and is sent to the operation processing unit 14 to perform various operations, and the operation result data is passed through the accumulator 16. Further, it is stored in the RAM 8 via the bus line 18 or is output to the outside via the I / O interface 20.

FIG. 2 is a schematic diagram of the storage circuit of the first ROM 4 in the digital signal processing circuit shown in FIG.
In the first ROM 4, the first main program 40a,
A plurality of main programs such as the second main program 40b are stored, and also subroutines 40n and 40m commonly used by these plurality of main programs are also stored.

FIG. 1 is a schematic diagram showing the structure of the program counter 2 in the digital signal processing circuit shown in FIG.
Each main program 40 is stored in the program counter 2.
a second ROM 3 in which a large number of operation menus each consisting of a set of a start address of a, 40b, ... And an execution mode are stored
0 is provided. Here from the outside this second ROM
When the address of 30 is designated, the operation menu stored at this address is read from the second ROM 30,
The execution mode in this operation menu is decoded by the decoder 32, and the address of the first ROM 4 (see FIG. 3) is generated according to the start address and the result of decoding by the decoder 32.
The instruction stored at this address is read from the first ROM 4. In this way, the external second ROM 3
By designating an address of 0, which main program of the plurality of main programs 40a, 40b, ... Therefore, as shown in FIG. 2, it is possible to store a plurality of main programs 40a, 40b, ... In one ROM. As described above, since the present embodiment has a plurality of main programs, the user can freely select and set the processing, and the digital signal processing circuit can have versatility.

[0011]

As described above, according to the present invention, a plurality of main programs are stored in the first storage means, and the main program stored in the first storage means is stored in the program counter. A second storage means in which a plurality of operation menus of the program counter, each of which is composed of a start address of the main program and an execution mode of the main program, are stored. Since the desired main program among the plurality of main programs stored in the one storage means is executed in the desired operation mode, the plurality of main programs are stored in one storage means with a simple configuration. Thus, it is possible to provide a digital signal processing circuit capable of executing a desired main program as needed.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a configuration of a program counter in the digital signal processing circuit shown in FIG.

FIG. 2 is a ROM in the digital signal processing circuit shown in FIG.
It is the figure which abbreviated the memory contents of.

FIG. 3 is a block diagram showing an example of a digital signal processing circuit according to the present invention.

[Explanation of symbols]

 2 program counter 4 first ROM 6 sequencer / decoder 8 RAM 10 address operation unit 12 multiplier 14 operation processing unit 16 accumulator 20 I / O interface 30 second ROM 32 decoder 34 counter

Claims (1)

Claim: What is claimed is: 1. A digital signal processing circuit comprising: a first storage means in which a program is stored; and a program counter for sequentially designating addresses of the first storage means. The storage means stores a plurality of main programs, and the program counter comprises a set of main program execution modes stored in the first storage means.
A second storage unit storing a plurality of operation menus of the program counter is provided, and a desired operation menu is stored in the first storage unit by externally designating a desired operation menu. A digital signal processing circuit, characterized in that the main program is executed in a desired operation mode.