JPS63204333A - Asynchronous signal generating circuit - Google Patents

Abstract

PURPOSE:To effectively respond when forced interruption is generated in an asynchronous circuit, by holding the output of a state flip-flop with an interruption state flip-flop responding to a holding timing from a holding information flip-flop sent by responding to the generation of the forced interruption. CONSTITUTION:The interruption state flip-flop 4 which inputs the output signal of the state flip-flop 3, and the holding information flip-flop 6 which sends the holding timing to the interruption state flip-flop 4 by responding to the generation of interruption in the asynchronous circuit, are provided. And by responding to the holding timing from the holding information flip-flop 6, the output signal of the state flip-flop 3 is held with the interruption state flip-flop 4 for a prescribed time. In such a way, it is possible to hold the operating state of an asynchronous signal generation circuit and an asynchronous signal 11, and to respond to the forced interruption in the asynchronous circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an asynchronous signal generating circuit, and more particularly to an asynchronous signal generating circuit having a state flip-flop that holds a state value that defines the operating state of the asynchronous circuit.

Conventionally, this type of asynchronous signal generation circuit has been constructed using a state flip-flop that holds a state value, a decoding circuit that decodes the output from the state flip-flop, and a state change i! that recognizes a state change. ! It consists of a state change recognition circuit and a state activation bin that outputs an input signal to the state change recognition circuit.When the asynchronous signal generation circuit is activated by the state activation bin, an asynchronous signal is automatically generated, and an asynchronous signal is automatically generated. The signal was changing.

In such a conventional asynchronous signal generation circuit, an asynchronous signal is automatically generated when a state activation bin is activated.
In addition, since the asynchronous signal was designed to change automatically, if a forced interrupt occurred in the asynchronous circuit, the operating state of the asynchronous signal generation circuit could not be maintained, and furthermore, the asynchronous signal could not be maintained. This has the disadvantage that it cannot handle forced interrupts in asynchronous circuits.

The present invention has been made to eliminate the drawbacks of the conventional circuits as described above, and an object of the present invention is to provide an asynchronous signal generating circuit that can cope with forced interrupts in an asynchronous circuit.

11. An asynchronous signal generation circuit according to the present invention has a state flip-flop that holds a state value that defines the operating state of the asynchronous circuit, and receives an output signal of the state flip-flop as an input. an interrupt state flip-flop; and a holding information flip-flop configured to send a holding timing to the interrupt state flip-flop in response to an occurrence of an interrupt in the asynchronous circuit; The interrupt state flip-flop is characterized in that the output signal of the state flip-flop is held for a predetermined period of time.

! 11 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one embodiment of the present invention includes a state activation bin 1, a state change recognition circuit 2 whose input is the output of state activation bin 1 x 1, and a state that defines the current operating state of an asynchronous circuit (not shown). Decodes the state flip-flop 3 that holds the value, the output CG from the state flip-flop 3, the interrupt state flip-flop 4 that inputs CI, and the outputs [)O, []1 from the interrupt state flip-flop 4. The circuit includes a decoder circuit 5 which outputs an asynchronous signal 11, and a hold information flip-flop 6 which sends hold timing to the interrupt state flip-flop 4. Here, the asynchronous signal 11 is a signal that controls the entire asynchronous circuit.

A state change occurs due to the asynchronous signal 11 and the output x1 of the state activation pin 1, and the state change recognized by the state change recognition circuit 2 is transmitted to the state flip-flop 3. Among the plurality of state flip-flops 3, the state flip-flop 3 to be changed is set or reset to determine the next state value. The outputs Go and CI of the state flip-flop 3 are input to the interrupt state flip-flop 4, and the output DO6 of the interrupt state flip-flop 4 is input to the interrupt state flip-flop 4.
D1 is decoded by the decoder circuit 5 to generate the next asynchronous signal 1.
Create 1.

Through this series of circuit operations, the next state value is set in the state flip-flop 3, and the next asynchronous signal 11 is outputted through the decoder circuit 5. Furthermore, the asynchronous signal E
When O becomes "1", normal asynchronous processing starts to be executed.

2 and 3 are time charts of one embodiment of the present invention. The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

When an interrupt occurs in the asynchronous signal generation circuit according to the embodiment of the present invention, as shown in FIG. The output bit A2 of the state change W1 recognition circuit 2 activates the output bit A2 to "1", and then the output bit A2 of the state change W1 recognition circuit 2 activates the output C1 of the state flip-flop 3 to "1", causing the interrupt state flip-flop 4 to activate the output bit A2 to "1".
The output D1 of is set to "1". The output D1 of the set interrupt state flip-flop 4 is decoded and
The asynchronous signal E2 becomes "1" and controls the entire asynchronous circuit.

When a certain period of time passes after the asynchronous signal E2 becomes "1", the output AO of the state change recognition circuit 2 becomes "1".

Next, the output AO of the state change recognition circuit 2 activates the output CO of the state flip-flop 3 to "1" and sets the output Do of the interrupt state flip-flop 4 to "1". The output Do of the set interrupt state flip-flop °4 is decoded, the asynchronous signal EO becomes "1", the entire asynchronous circuit is controlled, and the normal asynchronous processing 21 is started.

Similarly, when a certain period of time passes after the asynchronous signal EO becomes "1", the output A3 of the state change recognition circuit 2 becomes "1", the output C1 of the state flip-flop 3 becomes rOJ, and the asynchronous signal E1 becomes "1". ” and controls the entire asynchronous circuit, and when a certain period of time has passed since the asynchronous signal E1 became “1”, the output A1 of the state change recognition circuit 2 becomes “1”.
Therefore, the output CG of the state flip-flop 3 becomes rOJ, and the asynchronous signal E3 becomes "1" to control the entire asynchronous circuit.

Next, if an interrupt occurs while the asynchronous signal generating circuit according to the embodiment of the present invention is in operation, that is, at a timing when the asynchronous signal EO is "1", the state activation bin is set as shown in FIG. 1 output x 1 becomes "1" and asynchronous signal EO
Until the value becomes "1", the above-described operation is performed in the same way as in the time chart shown in FIG. 2 when no interrupt occurs.

Here, when the asynchronous signal @EO becomes "1" and an interrupt occurs, the output Y1 of the held information flip-flop 6 becomes "1".
”, the normal asynchronous processing 21 is executed first, and then the interrupt processing 22 is executed.

Here, when the asynchronous signal EO becomes "1", the output A3 of the state change recognition circuit 2 becomes "1" after a certain period of time, the output C1 of the state flip-flop 3 becomes rOJ, and the output of the held information flip-flop 6 becomes "1". The interrupt state flip-flop 4 is in a hold state for a certain period of time after Y1 becomes "1", that is, during the interrupt processing 22, and the values of the output CO and the output C1 of the state flip-flop 3 during the normal asynchronous processing 21, That is, "1" is held for a certain period of time, and the interrupt processing 22 is terminated during this period.

In one embodiment of the present invention, the time for the interrupt processing 22 and the holding time for the outputs CO and C1 of the state flip-flop 3 are made the same. During this time, state flip-flop 3
The outputs Go, CI, and asynchronous signals EO to E3 are prevented from changing.

When the holding period ends, that is, interrupt processing 2
2, the hold of the interrupt state flip-flop 4 is released, the output D1 of the interrupt state flip-flop 4 becomes "0", the asynchronous signal EO becomes "0", and the asynchronous signal E1 becomes "1". The subsequent operation is similar to the time chart shown in FIG. 2 when no interrupt occurs.

Incidentally, in one embodiment of the present invention, the holding time of the interrupt state flip-flop 4 is set to a fixed time, but an external command indicating the end of the interrupt processing 22 is outputted, and in response to this command, the interrupt state flip-flop 4 is held for a fixed time. 4 may be released, and is not limited to a certain period of time.

In this way, the outputs CO, CI of the state flip-flop 3
is held by the interrupt state flip-flop 4 in response to the holding timing from the held information flip-flop 6 that is sent in response to the occurrence of an interrupt in the asynchronous circuit, thereby controlling the operation and state of the asynchronous signal generating circuit. , and the asynchronous signal 11 can be held, making it possible to cope with forced interrupts in the asynchronous circuit.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the output of the state flip-flop is transferred to the interrupt state flip-flop in response to the holding timing from the held information flip-flop sent in response to the occurrence of a forced interrupt in the asynchronous circuit. This has the effect of being able to effectively respond to the occurrence of a forced interrupt in an asynchronous circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are time charts of one embodiment of the present invention. Explanation of symbols of main parts

Claims (1)

[Claims] An aperiodic signal generation circuit having a state flip-flop that holds a state value that defines an operating state of an asynchronous circuit, the circuit comprising: an interrupt state flip-flop that receives an output signal of the state flip-flop; a holding information flip-flop that sends a holding timing to the interrupt state flip-flop in response to an occurrence, and an output of the state flip-flop by the interrupt state flip-flop in response to the holding timing from the holding information flip-flop. An asynchronous signal generation circuit characterized in that a signal is held for a predetermined period of time.