JPS62133532A - Microprocessor - Google Patents

Abstract

PURPOSE:To make it unnecessary to provide a special timing adjusting circuit on the outside by extending a bit width of a first-in first-out buffer (FIFO) for an instruction code, and providing input/output terminals on the FIFO of an extended part. CONSTITUTION:In an extended part of a FIFO 3 for an instruction code, a break use FIFO 5 of one bit constitution having an input terminal 6 and an output terminal 7 is provided. The FIFO 3 inputs an instruction code from a data bus 1 through a bus interface 2, in accordance with the number of instruction codes which have been inputted to the inside. In this case, the FIFO 5 also inputs simultaneously a state which has been inputted to the terminal 6, and when an instruction executing part ends an execution of an instruction, and inputs the next instruction code to an instruction decoder 5, a state which has been inputted to the terminal 6 of the FIFO 5 at the time when its instruction code has been inputted to the FIFO 3 is outputted simultaneously to the terminal 7.

Description

[Detailed description of the invention]

1 First field of industrial disaster] Akira Honnoki relates to microprocessors with a first-in, first-out buffer in 1-1f. , -i
n-r i r! '+ 1n n 1. h u [
A microprocessor having an FTFO (hereinafter referred to as FTFO) reads an instruction code in advance during instruction execution, stores the instruction code, and supplies instruction codes 1 to 1 to an instruction decoder in the order of writing. Figure 4 shows an example of a conventional micro 10-seater 70-
In Figure 11, 1' is the data bus, 2' is the bus interface, and 3' is the FlF'0.4 for instruction code 1.
is an instruction decoder 8 is an output terminal for the operation status signal of F+r-'O. Next, the operation of the microprocessor shown in FIG. 1 will be explained. Depending on the number of instruction codes loaded into the FIFO 3', one instruction code is loaded into the FIFO 3' from the data bus l' through the interface 2'. Then, each time the instruction execution section finishes executing an instruction, the instruction code is sequentially sent from the PIF'03' to the instruction decoder. Furthermore, when a branch instruction is executed, all instruction codes in PIF03' are cleared, and a new instruction code starts to be read from the branch destination program address. In microprocessors since Uli, in order to inform the outside of the state of this FTFO 3, a Q signal is input to the instruction decoder 1.
The information that the command code was sent and the information that all the command codes in 171.03' were cleared were output from the output terminal 8 to the outside. In addition, in recent years, the use of emulation devices has increased when developing programs for microcomputers.

[1-1
It has functions such as reading and writing to block memory, reading and writing to registers in the microprocessor, etc. Among these functions, a method for realizing the function of stopping program execution at an arbitrary address is as shown in FIG.
The converter 52 connected to the register 51 inputs the address of the program to be stopped set in the register 51 and the address bus 5. ! A commonly used method is to compare 3 with the atto value from 1, and when they match, interrupt the micro 10 set source with a match signal 55. [Interlayer Point J to be Solved by the Invention When the conventional microprocessor described above uses the interrupt method shown in FIG. As shown in FIG. 6, an FI for storing instruction codes inside the microprocessor 63
The coincidence signal 55 from the comparator 52 is adjusted by the timing adjustment circuit 62 based on the FO operating status output signal 65 and the signal 66 that reads the command from the data bus, and the interrupt signal ( ) 7 is sent to the microprocessor processor 63. supplying and interrupting. BT's next microprocessor has timing: J! ,1
Problems arise when the adjustment circuit 02 becomes complicated.An object of the present invention is to provide a microprocessor that does not require a complicated timing adjustment 13. Means for Solving Problem 1 1 The microprocessor processor of the present invention includes a first-in, first-out buffer that reads an instruction code in advance during instruction execution, stores the instruction code, and sequentially outputs the instruction code in the order in which it is input; An instruction decoder that leverages the instruction food from the buffer is provided as an expansion buffer for the first-in-first-out rough 7, and the width of the first-in, first-out rough r is set to an arbitrary number of bits. It is composed of a first-in, first-out buffer for breaks having an expanded one-bit width, and input and output terminals of the first-in, first-out buffer for breaks γ. 1 Example 1 Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In Figure 1, 1 is the take hash, 2 is the hash interface, 3 is the instruction code I" f F=' O14 is the instruction decoder, and 5 is the extended part of the instruction code F' I F O. FIF for break in l-configuration
O16 is an input terminal of 1.''I)'0 for break, and 7 is an output terminal of Fll''0 for break. In the 114th step, P I F O3 for instruction code I~
stores the instruction code from the child bus 1 through the bus and interface 2 according to the number of instruction codes stored inside.At that time, the break code JFO5#J
At the same time, the manually applied state (low level or high level) is accommodated at the input terminal f+'. And, the command actual 1” part or life φ7
Terminate execution and store the next instruction code in the instruction decoder 4) 1!1, L'T for break when the instruction code is stored in 1fii instruction code F f F 03
The state (low level or high level) that is manually input to the input terminal 0 of the P O5 or is output to the output terminal 7 at the same time.Next, the emulator J of the embodiment is installed; Regarding the operation, please refer to Figures 2 and 3.
14j L explains/j-ru. Figure 2 is a block diagram of a circuit that stops program execution after executing a program at an arbitrary address in the microA L'7 emulation device based on Figure 1, and Figure 31 is shown in Figure 1. FIG. 2 is a block diagram of a circuit for stopping program execution after executing a program at an arbitrary address a plurality of times in a Micro 10 Setsuna emulation device. As shown in FIG. 2, the match signal 24 from the comparator 21 is sent to the break FI
If you input it manually to the input terminal 25 of FO, you can input 1 instruction = 1-de of the 7゛ trace you want to stop as the instruction code I'' T I
” At the same time as it reached 0, press F for break.
Match signal 24l from comparator 21 to TFO
or be taken in. The match signal 24 converts the instruction code of the area 1 to the address that you want to stop into the instruction code [-'TFO;/1J
)l\Fr for break when sent to instruction decoder
If this signal is output as a signal 26 from the output terminal of the TFO and is manually transferred to the interrupt input terminal 29, an interrupt will be generated when the AI/response haiku session that is desired to be stopped is executed. . In addition, as shown in Figure 3, there is a 12"ll7 for break.
0)) The signal 26 from the output terminal r- is input to the counter down clock input terminal 27 of the counter 23 (!l: #8
L, by manually inputting the hollow output 28 of the counter 23 to the interrupt input terminal 29 of the microprocessor 22, a zero stop instruction is executed for the number of times the counter 23 is set to zero plus 1. After executing, you can stop the program execution. 1. Utility of the invention 1 Hereinafter, explain the micro 10 cells of the present invention...
l is (j''r?r + for command code;
・/)・By expanding the width and providing FIFO input and output circle terminals in the expanded portion, special timing, iJ! ,1
! It has the effect of being able to stop the execution of Profurano 1 after executing the tf:S airless program without needing to have a u circuit. Brief Description of the Drawings Fig. 1 is a block diagram of an embodiment of the present invention, and Fig. 2 is a block diagram of an embodiment of the present invention.
Figure 3 is a block diagram of a circuit that stops 10-gram execution after executing an arbitrary program in the microprocessor emulation device shown in Figure 1. A block diagram of a circuit that stops program execution for one thread of execution. Figure 1 is a schematic diagram of an example of a Congo Song microprocessor. Figure 5 is a typical microprocessor of 10 cells.
A schematic diagram of the circuit for stopping program execution after execution of an arbitrary program in Sosa's emulation device. This is a block diagram of a circuit that stops 10-gram execution.6 1.1'... data bus, 2,2'... bus ink face, 3,3'... instruction = 7-1 ~ river I? I
O51...Instruction code, 5...L for break
I 170, []...Input terminal, 7.8...Output terminal -i4-. 21 、、、Compassi Ichita、22・Micro"１Kosetsusa、23、Power "'Nonta、()2...
Timing style! grass circuit.

Claims (1)

[Claims] A first-in, first-out buffer that reads an instruction code in advance during instruction execution, stores the instruction code, and sequentially outputs the instruction code in the order of input; an instruction decoder that decodes the instruction code from the first-in, first-out buffer; and an extension buffer of the first-in, first-out buffer. A microprocessor comprising: a break first-in first-out buffer having a bit width obtained by extending the bit width of the first-in first-out buffer by an arbitrary number of bits; and input and output terminals of the break first-in first-out buffer.