JPS6310445B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is a programmable controller (hereinafter referred to as
This relates to arithmetic processing units (abbreviated as PCs). Conventionally, there has been a device of this type as shown in FIG. In the figure, 1 is a word processing CPU such as a microprocessor (hereinafter abbreviated as W CPU), and 2 is an individual IC.
A 1-bit processing CPU (hereinafter referred to as B
(abbreviated as CPU), 3 is W CPU1 and B CPU2
Address bus switch 4 switches the respective address buses _A1 and _A2 of W CPU1 and B CPU2 to generate a common address bus _A3 , and 4 switches the respective data buses _{D1 and D2} of W CPU1 and B CPU2 to generate a common data bus.
A data bus switch generates _D3 , 5 is a sequence program memory, and 6 is a data memory for storing process inputs, process outputs, temporary storage values, etc. Next, the procedure of arithmetic processing by this device will be described. FIG. 5 shows an example of the program contents of the sequence program memory 5. It is assumed that the sequence program includes a mixture of 1-bit processing instructions and word processing instructions, and 1 step of both instructions consists of 2 bytes. In the example shown in Figure 5,
Step 0 is a 1-bit processing instruction (L ₀ , H ₀ ), Step 1 is a word processing instruction (L ₁ , H ₁ ), Step 2
consists of 1-bit processing instructions (L ₂ , H ₂ ). When processing this sequence program, in steps 0 and 2, address bus switch 3 and data bus switch 4 shown in FIG.
It is switched to the CPU2 side, and 1-bit arithmetic processing is executed under the processing of the B CPU2. Further, in step 1, both the address bus switch 3 and the data bus switch 4 are switched to the W CPU 1 side, and word arithmetic processing is executed under the processing of the W CPU 1. Note that arithmetic processing refers to decoding the contents of the sequence program memory 5, performing calculations based on the contents of the data memory 6, and storing the calculation results in the data memory 6. As explained above with examples, the conventional arithmetic processing units in PCs are W CPU and B CPU.
Since the 2-CPU system is adopted, switching means such as an address bus switch and a data bus switch are required, and a high-speed and inexpensive 1-chip or several-chip CPU is required for 1-bit processing.
Since there is no CPU, they are often constructed by combining individual ICs, which has the drawback of making the overall circuit complex and expensive. The present invention was made in order to eliminate the drawbacks of conventional arithmetic processing units in PCs as described above.
The purpose is to provide an inexpensive and compact PC processing device. An embodiment of the present invention will be described in detail below. FIG. 2 is a block diagram of a device according to an embodiment of the present invention. In the figure, 11 is for word processing.
The CPU is a microprocessor 8085 in this embodiment. 12 is a control program memory that stores a control program for the CPU 11;
3 is for temporary storage to temporarily store intermediate calculation results, etc.
RAM (random access memory), 14 is CPU1
For instruction storage to store the instruction code of 1
This is RAM, and its details will be explained in the operation explanation below. Further, 15 is a sequence program memory in which the user writes calculation procedures, etc., 16 is a data memory in which process input/output and temporary storage values, etc. are written, 17 is a 1-bit calculation circuit that executes 1-bit calculations, and 18 is a NOP ( NO-OPERA-
TION) is an instruction generation circuit. Note that A and D indicate the address bus and data bus of the CPU 11, respectively. Next, the arithmetic processing operations performed by the above device will be explained, and in addition, the features of the device of the present invention will be clarified. Using the control program written in the control program memory 12, the CPU 11 first stores an instruction code as shown in FIG. 6 in the instruction storage RAM 14 before starting the operation of the sequence program.
The stored contents are STA code for 1-bit processing instructions corresponding to each step of the sequence program,
If it is a word processing instruction, it is an RST code. Therefore, if the sequence program is as shown in FIG. 5, the code shown in FIG. 6 will be stored in the RAM 14. Furthermore, the microprocessor
In 8085, the STA code is a code for a write command, and the RST code is a code indicating a forced interrupt command. Next, in order to cause the CPU 11 to start calculating the sequence program, the control program branches to a specific address of the CPU 11, for example 8000# (# indicates a hexadecimal number). In this way, CPU 11
For example, if you start execution from 8000#, CPU1
A decoder (not shown in Figure 2), which is an attached circuit to address bus 1, decodes the lower bits of its address bus.
Chip select signals _CS0 to _CS3 are generated from _A0 and _A1 . FIG. 3 is a diagram showing the decoding function of this decoder 20. Here the chip select signal
CS ₀ to _{CS 3} are the lower bits of the address bus A ₀ , A ₁
This occurs when the conditions shown in the table below are met. CS ₀ A ₀ = 0 A ₁ = 0 CS ₁ A ₀ = 1 A ₁ = 0 CS ₂ A ₀ = 0 A ₁ = 1 CS ₃ A ₀ = 1 A ₁ = 1 For example, if the above specific address of CPU 11 is
If it is 8000#, CS ₀ at 8000#, CS ₁ at 8001#, CS ₂ at 8002#, CS ₃ at 8003#, CS ₀ at 8004# will occur. Each chip select signal
CS ₀ , CS ₁ ... are configured to have the following command functions. That is, at CS ₀ , the instruction storage RAM 14, at CS ₁ , the lower byte part of the sequence program memory 15 (L ₀ , L ₁ , L ₂ in Figure 5).
...) At CS ₂ , the upper byte part of the sequence program memory 15 (H ₀ , H ₁ , H ₂ in Figure 5)
...) Each of the NOP instruction generation circuits 18 is selected at CS ₃ , and its contents are sent to the data bus D. As a result, in 8000# to 8002#, STA, L ₀ and H ₀ are respectively sent to the CPU 11 via the data bus D. Here, STA, L, and H are microprocessors.
In the 8085, this is a write command at address HL. STA,
The L and H instructions are executed in machine cycles M ₁ to _{M 4} as shown in FIG. Timing M ₁ ,
Each code of STA, L, H is read at M ₂ and M ₃ , and it is recognized that it is an STA, L, H instruction, and at timing M ₄ , the address bus is written to write data to address HL. The contents of HL are sent to A ₀ to _{A 15} . In the example of the sequence program shown in FIG. 5, the content of this HL is 1-bit processing instruction 2 (H ₀ , L ₀ ). In this way, the 1-bit arithmetic circuit 17 operates on the address bus _A0 to _A15.
A 1-bit operation is executed based on the 1-bit processing instruction 1 (H ₀ , L ₀ ) sent out at timing _M4 . Next, at 8003#, the chip select signal _CS3 is generated as described above, the NOP instruction generation circuit 18 is selected, and the NOP instruction code is sent out. The NOP instruction is a no-processing instruction of the CPU 11. Further next
In 8004#, the chip select signal CS ₀ is generated again and the instruction storage RAM 14 is selected.
Since the RST code is stored in the RAM 14 as shown in FIG. 6, this RST code is sent to the CPU 11. The RST instruction is
This is an interrupt processing start command for the CPU 11, and executes an interrupt processing program from a specific address in the control program memory 12. Here, the interrupt processing program is actually a program that recognizes word processing instructions L ₁ and H ₁ and performs word processing. When the execution of this program is completed, the CPU 11 returns to 8008#. Thereafter, from 8008#, each code is sequentially selected such as STA, L ₂ , H ₂ , NOP, etc., and 1-bit operation and word processing are executed according to the contents of the sequence program. FIG. 7 summarizes the above processing and shows the flow of calculations in this device. As explained above, in this device, 1-bit processing instructions and word processing instructions in a sequence program are written in advance as separate codes in the instruction storage RAM 14, and input to the CPU 11 as instructions with different meanings. be done. That is, 1
In the case of a bit processing instruction, a write instruction (STA instruction) of the CPU 11 is selected, and this instruction is sent to the CPU 11. The CPU 11 uses the machine cycle of this instruction to cause the 1-bit arithmetic circuit 17 to execute 1-bit arithmetic processing. On the other hand, when it is a word processing instruction, the forced interrupt processing instruction (RST instruction) of CPU11 is used.
is selected, and the CPU 11 executes an interrupt processing program, in this case a word processing program. Therefore, in this device, 1-bit arithmetic processing and word processing can be performed at the timing of one CPU, and a 1-bit processing CPU is not required. As explained above with reference to the embodiments, according to the present invention, one CPU (word processing CPU) can perform 1-bit arithmetic processing and word processing.
For 1-bit arithmetic processing, which is expensive and complicates the circuit.
CPU is not needed. Furthermore, switching means such as address bus switches and data bus switches are also obviated, and an inexpensive and compact PC arithmetic processing device can be obtained. Although the above-described embodiment of the present invention uses the STA and RST instructions of the microprocessor 8085, it is of course possible to implement the same using other microprocessors. Also,
Although the sequence program example shown in FIG. 5 is explained using 2 bytes per step, it is of course possible to execute the program in the same manner even if the number of steps is 4 or 6 bytes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional device of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a decoder incorporated in the device shown in FIG. 2. The circuit diagram, Figure 4 is STA
Timing diagram showing machine cycles of instructions, No. 5
The figure shows an example of a sequence program.
This figure shows an example of the storage contents written in the instruction storage RAM shown in FIG. 2, and FIG. 7 is a flowchart showing an example of sequence operations performed by the apparatus shown in FIG. 2. 11...CPU, 12...Control program memory,
13...RAM for temporary storage, 14...For instruction storage
RAM, 15...Sequence program memory, 1
6...Data memory, 17...1-bit arithmetic circuit.

Claims (1)

[Scope of Claims] 1. A CPU mainly for word processing, which is composed of a microprocessor, etc., a control program memory that stores a program to control this CPU, and the above-mentioned CPU.
A temporary storage RAM that temporarily holds intermediate calculation results and data, etc. in the CPU, a sequence program memory that writes calculation procedures, etc., an instruction storage RAM that stores the instruction code of the CPU, and a memory 1 that performs 1-bit calculation processing. It is equipped with a bit arithmetic circuit and a data memory for storing process input/output and temporary storage values, etc., and the control program memory recognizes the 1-bit processing instruction and the word processing instruction in the sequence program memory and stores them separately. A program is written for converting the code into a code given by the CPU and storing it in the instruction storage RAM, and furthermore, the CPU has a code in which the signal sent from the instruction storage RAM corresponds to a 1-bit processing instruction. The 1-bit arithmetic circuit is activated at one timing during a machine cycle when a write command is issued and this command is executed, and the RAM for storing the command is activated.
1. An arithmetic processing unit for a programmable controller, characterized in that the arithmetic processing unit of a programmable controller is incorporated to issue a forced interrupt processing command and execute a word processing program when a signal sent from the controller has a code corresponding to a word processing command. 2 In the control program memory, 1-bit processing instructions in the sequence program memory are converted into CPU write processing instruction codes, and word processing instructions are converted into CPU forced interrupt processing instruction codes and stored in instruction storage RAM. 2. An arithmetic processing device for a programmable controller according to claim 1, wherein a program for storage is written. 3 The CPU is equipped with a decoder as an attached circuit to decode the lower bits of the address bus and generate a chip select signal, and the generated chip select signal selects the instruction storage RAM and sequence program memory, and the contents are transferred to the CPU. 2. An arithmetic processing device for a programmable controller according to claim 1, wherein the processing device is configured to send data to a programmable controller. 4 The CPU is a microprocessor 8085, and 1-bit processing instructions in the sequence program are converted to STA codes by the control program, and word processing instructions are converted to RST codes and stored in the instruction storage RAM. An arithmetic processing device for a programmable controller according to claim 1, characterized in that: