JP2618703B2 - High-speed operation processing method of programmable sequence controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-speed operation processing method for a sequence controller.

(Prior Art) Conventionally, a hardware sequencer that executes a sequence program at high speed has already been put to practical use. However, there has been no practical use of a hardware sequencer for executing a complicated instruction for calculating the rotation direction of a rotating body. Also, a software sequencer that executes a complicated instruction by a microcomputer has been put to practical use, but its operation speed is several times to several tens times slower than a hardware sequencer. Nothing is fast and sophisticated.

(Problems to be Solved by the Invention) The conventional programmable sequence controller can process complicated instructions, but has a problem that the speed is slow.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problem, and an object of the present invention is to provide a high-speed arithmetic processing method capable of speeding up arithmetic processing of a programmable sequence controller and executing a complicated instruction.

(Means for Solving the Problems) In order to achieve the above object, the present invention achieves the above object by compiling and executing a complicated instruction of a programmable sequence controller by a microprocessor, and executing a simple instruction by a column cyclic operation unit (hardware). Decrypt and execute. When the microprocessor distinguishes between complex instructions and simple instructions,
The operation processing of the instruction is delayed by the execution time of the determination program. In order to solve this problem, a memory for storing a machine language of a microprocessor or an I / O read microprocessor corresponding to a sequence source program on a one-to-one basis, and a memory for storing a sequence program for performing an operation by a column cyclic operation unit And the microprocessor executes the machine language. When the machine language is executed, an address for reading the memory or I / O is output from the microprocessor, and a sequence program in which the column cyclic operation unit performs the operation using this address is read, and
By the operation of the control unit which starts the column cyclic operation unit and executes the next machine language by the column cyclic operation completion signal, the microprocessor executes a program for transferring and starting the sequence program to the column cyclic operation unit. It is unnecessary. Complex instructions can be processed in a microprocessor by inserting a subroutine call instruction as a machine language.

(Operation) Therefore, according to the present invention, for one sequence source program, a memory for decoding and executing by a microprocessor and a memory for decoding and executing by a column cyclic operation unit are provided. Programmable sequence controller capable of high-performance and high-speed processing by executing simple instructions at high speed in the column cyclic operation unit and processing complex instructions by the microprocessor by the execution sequence control unit of the column cyclic operation unit. Can be realized.

(Embodiment) FIG. 1 shows main blocks of a programmable sequence controller which executes a high-speed operation processing system according to an embodiment of the present invention. In FIG. 1, 1 is a microprocessor (CPU), 2 is a decoder, and 3 is ▲.
The generation circuit 4 is a read-only memory, and has a one-to-one correspondence with the sequence source program, and stores a machine language to be decoded and executed by the microprocessor. Reference numeral 5 denotes a read-only memory, which is decoded by the column cyclic operation unit.
Stores the instruction to be executed. Reference numeral 6 denotes a column cyclic operation unit, 7 denotes a dual port memory (RAM) for storing relay contact and coil information and the like used in the sequence program, and 8 denotes an input / output unit (I / O).

FIG. 2 shows the relationship between the ladder diagram of this embodiment and a sequence source program corresponding to the ladder diagram. FIG. 3 shows the correspondence between the sequence source program in this embodiment, the instruction words decoded and executed by the microprocessor (in assembler description in FIG. 3), and the instruction words decoded and executed by the column cyclic operation unit. I have. In FIG. 3, reference numerals 9, 10, 11, and 12 are bit operation instructions, and all the languages decoded and executed by the microprocessor are compiled into memory transfer instructions.

FIG. 4 shows details of the relationship between the sequence source program and the command words decoded and executed by the column cyclic operation unit in this embodiment.

Next, the operation of the above embodiment will be described. In FIG. 1, the CPU 1 decodes and executes a machine language corresponding to the sequence source program in the ROMA 4 on a one-to-one basis, and
It controls the entire system, such as service to O8 and alarm processing, and executes complicated instructions that cannot be processed by the column cyclic operation unit, for example, the calculation of the rotation direction of the rotating body. A simple instruction for performing a bit-wise operation is decoded and executed by the column cyclic operation unit 6.

In this embodiment, 68000 is used as the microprocessor (CPU).
The example which used is shown. CPU 68000 can be memory or
Address data and control line (I / O read / write)
▼), and when the signal ▲ ▼ is input from the outside, the control line (▲ ▼) is turned off and the execution of the next command is started. Using this function, the decoder 2 and the ▼ generating circuit 3 control whether the operation of the sequence program is performed by the microprocessor or the column cyclic operation unit.

In FIG. 3, the correspondence between the sequence source program and the language executed by the microprocessor will be described first. The bit operation instructions 9, 10, 11, 12 are all compiled into memory transfer instructions. In this embodiment, after reading the contents of the memory associated with the A ₀ register D ₁ register are compiling instructions that 2 increasing the content of A ₀ register. Multiply instruction
13 is compiled into a subroutine call instruction and a constant definition instruction for execution by a microprocessor. The sequence source program end instruction 14 is compiled from a subroutine into a return instruction. Next, the correspondence between the column cyclic operation unit execution language and the sequence source program will be described. The compilation into the column cyclic operation unit execution language is performed only by the bit operation instruction.

In FIG. 1, a sequence program is executed as a subroutine of a microprocessor. Accordingly, the microprocessor makes a subroutine call for the head address of the language that the microprocessor decodes and executes, corresponding to the sequence source program stored in the ROM 4 on a one-to-one basis. The A ₀ register before subroutine call ROM5
Set the start address of Therefore, when the microprocessor executes the first memory transfer instruction to output the contents of A ₀ register to the address bus. The address data is decoded by the decoder 2, the ROM 5 is selected, an instruction is output to the column cyclic operation unit 6, and the operation is started.
After executing the received command, the column cyclic operation unit 6 outputs a column cyclic operation completion signal to the 発 生 generation circuit 3. The 発 生 generating circuit 3 outputs ▼ to the microprocessor (CPU) 1. C
When receiving PU, PU1 reads the next command from ROM4 and repeats the same cycle as above. When the CPU 1 executes the return instruction in the subroutine, it completes one cycle of the sequence program.

As described above, according to the above-described embodiment, a programmable sequence controller of a high-performance and high-arithmetic process capable of completing a bit operation instruction in one instruction execution cycle of a microprocessor and executing a complicated instruction is realized. be able to.

Stores instructions to be executed by the column cyclic operation unit
If the bit width of the ROM is further increased from 16 bits, the number of relay contacts and coils that can be handled at the same speed can be increased.

In the above embodiment, the ROM4 and the ROM5 are represented by different ROMs, but may be the same ROM. Of course, storage means other than ROM, for example, RAM may be used.

(Effects of the Invention) As is clear from the above embodiment, the present invention uses a microprocessor and a column cyclic operation unit to process simple instructions at a high speed in the column cyclic operation unit, and processes complicated instructions by the microprocessor. This has an effect that a high-performance and high-speed sequence controller can be realized. In addition, since all processes are synchronized with the instruction cycle of the microprocessor (CPU), many other processes such as display, other than sequence processing, can be performed by one CPU like the built-in programmable sequence controller of the numerical controller. It is particularly effective for performing applications.

[Brief description of the drawings]

FIG. 1 is a main block diagram of a programmable sequence controller in one embodiment of the present invention, FIG. 2 is a diagram showing a relationship between a ladder diagram and a corresponding sequence source program in the embodiment, and FIG. FIG. 4 is a diagram showing a correspondence between a command word decoded and executed by a processor and a command word decoded and executed by a column cyclic operation unit. FIG. 4 shows a sequence source program and a command word decoded and executed by a column cyclic operation unit. FIG. 1 ... CPU, 2 ... Decoder, 3 ... ▲ ▼ Generation circuit, 4,5 ... Read-only memory (ROM), 6 ... Column cyclic operation unit, 7 ... Dual port memory (RA
M), 8 ... I / O, 9, 10, 11, 12 ... bit operation instruction, 13 ...
... multiplication instruction, 14 ... sequence source program end instruction.

Claims (2)

(57) [Claims] 1. A column cyclic operation unit for decomposing a relay ladder circuit into contact information and branch information in correspondence with a switch matrix, performing repetitive operation for each column to perform output information processing, and a column cyclic operation A memory for storing a sequence program for performing an operation by the unit, a memory for storing a machine language of a memory or an I / O read microprocessor corresponding to the sequence source program on a one-to-one basis, and a micro-processor for executing the machine language. A sequence program is read from a sequence program storage memory unit by a memory or an I / O read address output when the microprocessor executes machine language, a column cyclic operation unit is started, and a column cyclic operation is completed. The microprocessor executes the next machine language according to the signal. Fast arithmetic processing method of the programmable sequence controller, characterized by executing a sequence program in one instruction within an execution cycle of the sub. 2. The programmable sequence controller according to claim 1, wherein a bit operation instruction is stored in a memory as a memory or I / O read machine language, and a complicated instruction is stored in a memory as a subroutine call machine language. High-speed processing method.