JPS63148303A - Arithmetic processing system for programmable sequence controller - Google Patents

Abstract

PURPOSE:To quickly process the column cyclic operation with software by compiling instruction words of a relay ladder diagram into instruction words of a CPU. CONSTITUTION:An instruction word having parameters which correspond to respective elements of a relay ladder in 1:1 is generated. (n) indicates 128-kinds of byte address 00H-7FH of all contacts, and (b) indicates 8 kinds of bit address 0-7 of all contacts. The instruction word to load parameters of said instruction word to registers (omitted in the figure) and instruction words to call subroutines of a sequence program are generated, and these instruction words are compiled.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a programmable sequence controller (hereinafter referred to as a PC) that programmably executes sequence control of various automated equipment, and particularly relates to a programmable sequence controller (hereinafter referred to as a PC) that programmably executes sequence control of various automated equipment, and in particular, The present invention relates to an arithmetic processing method for a programmable sequence controller that can perform arithmetic processing on a PC having a click arithmetic function at high speed by processing column cyclic arithmetic using software instead of using hardware.

[Conventional technology]

Generally, when creating a sequence program consisting of a group of instructions on a program to replace a relay ladder circuit on a PC, it is necessary to carefully examine the corresponding relay ladder circuit itself and create the program while considering the order of execution of the instructions. . This has the disadvantage that as the relay ladder circuit becomes more complex, the creation of the sequence program also becomes more complicated.

In order to overcome these problems, a column knife click calculation system has been proposed that allows mechanically easy programming of any rail ladder circuit, no matter how complex (Japanese Patent Application Laid-open No. 147203/1983). This calculation method includes, for example, a calculation unit shown in FIG. 9. In FIG. 9, a shift register 101 is a first storage means for inputting contact information, a shift register 102 is a second storage means for inputting branch information, and a shift register 103 is a first storage means for inputting contact information, and a shift register 103 is a first storage means for inputting contact information. 3rd set to logical value 1
is a storage means, and Ω performs logical operations for one column of the relay ladder circuit in response to the output from the third storage means and the outputs from the first and second storage means, and the result is Gate means configured to be applied to the third storage means. Command words C11, C and C31 are the ninth
Contacts C1C and C of the relay ladder circuit shown on the left side of the diagram
31, and instructions IB11 and B21 correspond to branches B and B21 of the relay ladder circuit, respectively. In the conventional system, as is clear from the logic circuit of the gate means Ω, for example, the instruction word C21 of the contact point is the instruction word C21 of the contact point in the same column and the adjacent row, and the instruction words C are branch instructions 1811 and 8.
It is set to be input to the third storage means as an output for calculating the logical sum of the logical products C-8 and C-31·B21, which are false as 21. This input is fed back to the command word C22 of the contact in the second column and a logical product is taken, and the same operation as the command word C21 of the contact in the first column is repeated and continued for the contact command HC2□. . In this way, the calculation is executed simply by loading the contact instruction IC and the branch instruction HB, so that high-speed calculation is possible. In order to reduce the PC scan time by utilizing the characteristics of column knife-click calculations, relay ladder calculations are processed by a column cyclic calculation unit consisting of hardware, and I10 access, alarm detection, Regarding checkers, peripheral device services, etc., a PC system in which processing is performed by a CPU has been developed.

[Problems that the invention solves]

However, P
In C, in order to effectively operate the arithmetic unit with the hardware configuration shown in FIG. 9, a timing generation circuit for repetitive scanning, a separator between the CPLI and the column cyclic arithmetic unit, etc. are required, and the overall device The problem arose that it was expensive and unsuitable for small-scale PCs. In addition, in the conventional method of performing only CPU processing, not only the above-mentioned difficulties in creating a sequence program, but also the fact that the instruction words of the sequence program are decoded one by one.
Since an interpreter method, which is an interpreter routine that sequentially reads input/output data (I10 data), is used, there is a problem in that these processes take a lot of time and the scanning time cannot be shortened.

Therefore, an object of the present invention is to omit the branch instruction word in the conventional column cyclic operation method, create a new instruction word for the contact point in place of it, and to The object of the present invention is to provide an arithmetic processing method that is suitable for small-scale and low-cost PCs by processing cyclic arithmetic operations using software.

[Means for solving problems]

The arithmetic processing method of the programmable sequence controller according to the present invention is to make the relay ladder circuit correspond to a switch matrix, and perform logical operations sequentially from the left end column of the column information and row information circuit toward the right output section side. In a programmable sequence controller equipped with a column cyclic calculation function configured to stack up the output states of the relay ladder and execute the sequence program by calculating the state of the output in the corresponding row, a command word regarding the parameter corresponding to each element of the relay ladder; Create a command word for a contact point related to branching of a relay ladder, a command word for loading the parameter into a register, and a command word for calling a subroutine of a sequence program, and pile up these command words to form a sequence program. It is characterized by

In the arithmetic processing method described above, the compiled instructions that form the sequence program include instruction words that load parameters related to data such as relays, output coils, timers, counters, etc. into registers, and subroutines that indicate processing procedures for the parameters. It can be composed of an instruction word to call, and an instruction word to call a subroutine that performs the parameter logical operation for one column by an instruction indicating the column boundary of the column cyclic operation.

[Effect]

According to the arithmetic processing method of the programmable sequence controller according to the present invention, each element of the relay ladder is
Convert the parameters of the input part and output part into command words using the correspondence, and create an command word to load the parameters into the register and a command word to call the sequence program's command, and then convert these command words into command words. By compiling, a sequence program can be easily created by the CPU.

〔Example〕

Next, an embodiment of the arithmetic processing method of the programmable sequence controller (PC) according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block circuit diagram of a PC implementing the arithmetic processing method of the present invention. It is shown in Figure 1, reference mark @10 is C.
PU (for example 780A), 12 is memory, 14 is ■10
interface, 16; peripheral device interface, 18;
2 indicates an alarm display, 20 indicates an I10 device, and 22 indicates a peripheral device. Therefore, in the circuit of this embodiment, no special column cyclic calculation section is provided. Next, we will explain a program example when using an 8-bit CPU (Z80A). Note that because it is an 8-bit CPU, it is limited to column cyclic calculations of input parameters and 8 output parameters related to a 8-row x 11-column rail ladder. be done.

First, the command words of parameters that correspond one-to-one to each element of the relay ladder are as shown in FIG. Second
In the figure, n indicates the byte address of all contacts,
There are 128 bits from OOH to 7FH, and b indicates the bit address of all contacts, and there are 8 bits from 0 to 7.

The map of I10 data is 1 byte 8 as shown in Figure 3.
Stored in bits. Storing in 1 byte and 1 bit is considered to require less memory capacity, but requires processing to convert to 8 bits, which increases processing time. In the command word (AND C0NNECT) and (AND C0N
NECT TOP) is a new contact instruction word that replaces the conventional branch instruction word. In addition, the commands □---, which does not indicate an unconditional connection, and ・, which indicates no connection, are replaced with a contact a and a contact b command of a specific address. These are essentially zero. These instruction words are used by the CPU (Z8
CPtJ (Z80A)
) and stored as shown in the I10 data memory map of FIG. For example, the following is compiled:

Compiled into LD L, X0OL.

CALL ANDO Here, X0OL indicates the byte address containing xooo. LD is an instruction word for loading parameters into a register, and 0ALL is an instruction word for calling each processing program, such as a subroutine. In addition, a compilation example is shown below.

Output car〇--mill YO15→LD L, YOIL
To C8LL 0UT5 In addition, the branch information is written at the end of the 1-column statement from BROO to B indicated by the subroutine called during compilation in Figure 4.
Processing is performed according to each of the 128 branch patterns of RFE.

As mentioned above, the TOP instruction indicating the end of this column indicates the column boundary, and the output result of the previous column [shown in the C register] and the input result of the contact point of this column [shown in the B register] are combined. The compiled instruction word B is a subroutine that performs a logical product, then performs a logical sum using the branch pattern for this column and one column, and stores the new data in the C register.
It is R30. Furthermore, END is an output end command word and sets the input contact register [B register] to 0 and the output register [C register] to 0FFH.

for example CALL 0UT2 10 BC, 0OFFH is compiled with

Latch timers, counters, function instructions, etc. are also compiled in the same way, for example as shown below.

CALL FOOO Therefore, an example of a subroutine program is shown in FIG. 4 as follows.

AND OLOA, [HL] RR8 ← Let RET in the contact register ← Return (In this ANDO subroutine, it is assumed that the upper 8 bits of the start address of the I10 memory are stored in the 1 register of [HL]. Also, RR is This is a rotation shift command.] NANDI LD A, [HL] CCF
←Pit inversion RRB ←Set in contact register ET 0UT5 LD A, [lIL RL C←Output result retrieval JRC, 0UT5. ON ← Output ON ET AND 38H ← Bit 3, 4.5 check RETZ
←Bits 3, 4.5 all 0 The numbers of each bit, 3, 4, 5, are as shown in FIG.

The subroutine programmed in this way is shown at 23 in Figure 4 as a subroutine called when compiled.
Seven types are shown.

Next, the above-mentioned arithmetic processing method of the present invention will be explained by showing a specific example. FIG. 6 shows an example of a beam relay ladder diagram, and a case where a command word is created based on this relay ladder diagram will be described. That is, when converting each element of the relay ladder shown in Fig. 6 into a command word, the contact data x000 etc. of the input part are arranged in order from the bottom to the top, and the parameters of the output part are arranged in order from the top to the bottom. Then, it is converted into an instruction word as shown in FIG. In this way, the converted instruction word is compiled into a compiled instruction word as shown in FIG. Therefore, P
, C, the CPU repeatedly executes a program consisting of compiled instructions shown in FIG.

〔Effect of the invention〕

As is clear from the embodiments described above, according to the calculation method of the sequence controller according to the present invention, column cyclic calculations can be processed at high speed by software by compiling the command words of the relay ladder diagram into the command words of the CPU. This makes it possible to obtain an arithmetic processing method suitable for small-scale, low-cost PCs.

Although the preferred embodiments of the present invention have been described above, it goes without saying that various design changes can be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a programmable sequence controller that implements the arithmetic processing method according to the present invention, and FIG.
The figure is an explanatory diagram of command words corresponding to the relay ladder diagram adopted in the method of the present invention, and FIG. 3 is the I1 adopted in the method of the present invention.
4 is an explanatory diagram of the memory map of 0 data, FIG. 4 is an explanatory diagram of the subroutine called at the time of compilation adopted in the method of the present invention, and FIG. 5 is a diagram of the number of bits in the program of the subroutine adopted in the method of the present invention. 6 to 8 are explanatory diagrams showing the relationships, and FIGS. 6 to 8 are an example showing compilation of instruction words in the method of the present invention, FIG. 6 is a beam rail ladder diagram, and FIG. 7 is a conversion diagram to instruction words, FIG. 8 shows a conversion diagram into a compiled instruction word, and FIG. 9 is a block circuit diagram of the main part of a conventional column cyclic arithmetic unit. 10...cpu i 2...memory 1
4...I10 interface 16...Peripheral device interface 18...Alarm display 20...I10 device 22
... Peripheral device 101 ... Shift register (first storage means) 102
...Shift register (second storage means) 103...
Shift register (third storage means) FIG, 2(a) FIG, 2(b) FIG 3 FIG,! . Total of 237 types of bits) J# Eka part one stab -' X0O4 TOP-e← X0O1 TOP←Hee L →←X0O4(ro ALL NQ'#foot(→YOIO(
Confucianism, IIL

Claims (2)

[Claims] (1) The relay ladder circuit is made to correspond to the switch matrix, and logical operations are stacked sequentially from the leftmost column of the column information and row information circuit toward the output section on the right side, and outputs in the corresponding rows. In a programmable sequence controller equipped with a column cyclic calculation function configured to calculate the state of a relay ladder and execute a sequence program, command words related to parameters corresponding to each element of a relay ladder, and command words of contacts related to branching of the relay ladder. , an arithmetic processing for a programmable sequence controller characterized in that an instruction word for loading the parameters into a register and an instruction word for calling a subroutine of a sequence program are created, and these instruction words are compiled to form a sequence program. method. (2) In the arithmetic processing method described in claim 1, the compiled instruction words forming the sequence program are instruction words for loading parameters related to data of relays, output coils, timers, counters, etc. into registers. , a programmable sequence controller comprising an instruction word that calls a subroutine that indicates a processing procedure for the parameters, and an instruction word that calls a subroutine that performs the parameter logical operation for one column with an instruction that indicates the column boundary of the column cyclic operation. calculation processing method.