KR900005548B1 - Programmble controller - Google Patents

Abstract

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Description

[Name of invention]

Programmable controller

[Brief Description of Drawings]

1 is an explanatory diagram of a magnetic holding circuit.

2 is an explanatory diagram of transition of a unit process in order control.

3 to 9 are process explanatory diagrams of the present invention.

10 is a block diagram showing the main parts of a programmable controller according to an embodiment of the present invention.

11 is a format diagram of a programmer stored in the program memory section of the controller described above.

12A and 12B are explanatory diagrams of logical transmission in the input / output internal relay circuit.

13A is an explanatory diagram of the operation of the robot hand.

13B (a)-(i) are explanatory diagrams which decomposed the operation in each step.

13C is a flow chart of its operation.

14 is a block diagram showing circuit conditions for inputting into a programmable controller for executing the above-described process.

Fig. 15 is a block diagram showing circuit conditions input to a conventional apparatus (ladder method) for carrying out the above-described steps.

16A and 16B are explanatory diagrams of logical transfers in FIG.

17 is a block diagram showing the main parts of a programmable controller according to another embodiment of the present invention.

18 is an explanatory diagram showing the contents stored in the process address storage unit.

19 is a flowchart showing the operation of the programmable controller of FIG.

Detailed description of the invention

Technical Field of the Invention

The present invention relates to a programmable controller for operating a control system such as a machine tool in a certain process sequence.

[Background of invention]

Programmable controller that controls controlled systems such as machine tools to operate in a certain process order, and has a program memory unit to write necessary control contents, and to standardize design and manufacture. In recent years, programmable controllers that can easily cope with changes in the specification of the sieve and the change of the process order have been diversified. Programming of this kind of device is executed by writing a program required by the operation of the setting key provided on the operating table to the program storage unit. In the conventional apparatus, however, it is necessary to design a relay circuit in order to make a basic programming setting in such programming. In other words, the circuit was designed using a contact or solid state relay, and the program was obtained by encoding the circuit diagram, blooleam algebra, and code. Therefore, although the design and manufacture of the programmable controller itself have been standardized, the design work of the relay circuit is similar to the design of a conventional sequence controller using a relay as a main component in the programming of the controlled system. There was a problem in that it would reduce the benefits of standardization. In addition, in the case of rewriting the program to change the operation sequence and the specification of the controlled object at the demand price, the design of the relay circuit is similarly required, and the advantage that the device can be widely used can be sufficiently determined. There was a flaw that there was no. Furthermore, since the capacity of the program cannot be calculated until after the design of the relay circuit is completed, there is a problem that it causes a delay even in the specification of the programmable controller.

[Initiation of invention]

SUMMARY OF THE INVENTION The present invention has been accomplished in view of the above circumstances, and an object thereof is to provide a programmer controller which solves the above-described problems by making the configuration programmable according to the operation of the controlled object.

Another object of the present invention is to provide a programmer controller which speeds up the execution processing time of a program in the controller described above.

SUMMARY OF THE INVENTION The present invention has been accomplished in view of the fact that control is constituted by a combination of unit processes, and a flag storage means (multiple) having a function of storing the state of the unit process in correspondence to a running unit process (multiple) And a flag of the flag corresponding to the contents of the process flag address in the program read out in time divisions from the program memory, and the flag is turned on. If present, control of the unit process (single or plural) corresponding to the plaque is carried out, and at the end of each unit process, a program (content of the following process) instructing the next unit process is used as a program. To make the transition to freedom.

By the way, since the present invention employs a program method, i.e., a process method, which executes a control operation for each unit process as described above, it is required to output the output output in one process even within another process. For this reason, the output instruction (OUT instruction) for the same output number is described anywhere in the program. For example, in a rudder type program, only one output command for an output number appears in the program, and the present invention provides a condition matching control in which only one output is turned on or off. In the process method related to the above, the operation of any output can be described any number of times in any process. Therefore, in describing the control system, the ease of programming has a distinct advantage over the former. This fact can also be said that the flow of operation of the control system is easier to understand in the third party. Details of this will be described later.

In this invention, in order to realize the outstanding point of a process system, ie, the function which can describe the output command about the same output number in a process unit, the problem of following (a)-(c) must be solved.

(a) When using an output in two places in one process and another, the output command for this output is described in two places in the program. If the output is turned on in one process, how should the output be handled when the output is turned off in another process?

(b) In the process method, the process can be processed only when the process is on, but when this process is off, all the processes in the process are operated so that they cannot be executed. At this time, if the output command is operating to turn on some output, when is the process turned off, when is the output output by this output command turned off?

In order to solve the problems of (a) and (b) described above, the output operation to the outside is completed after the completion of one scan [Input Transfer (Read) -Program Execution (Read and Compute)]. We can think of turning off the entire output afterwards. In this way, the operation of turning off the output does not need to be executed by an output instruction (OUT instruction) in the program. For example, even if a process controlling an output is turned off, the output is completed after one scan is completed. You can always turn it off.

(c) However, if the output is always turned off at the end of one scan, the self-holding program cannot be organized as shown in FIG. That is, in a process, when the input A is turned on, the output X is turned on, and the output X continues to be turned on even when the input A is turned off by checking the output X. In order to turn off this output X, this process should just turn off. However, if this program is executed in the above-described manner, self-maintenance is not possible. That is, during some scan, input A is turned on (command 2), and as a result, output X is turned on by the OUT command 4.

When one scan ends, the outputs are all turned off. Therefore, if the input A is turned off in the next scan, the instruction 2 is turned off, and the ORX of the instruction 3 is also turned off. Therefore, the output X is turned off. Also becomes off.

The problem of the above-mentioned (a)-(c) is solved by the description of logical transfer in this invention, The detail is demonstrated later.

Next, the programmer controller according to the present invention adopting the above-described logic transfer technique is stored in the program storage unit, and the instruction counter registers a series of programs composed of a plurality of processes each having a process number for each fixed control unit. In a programmable controller of a control method that reads, interprets, and executes according to an address indicated by), each process unit includes a process number, a logic operation and / or a data operation instruction, a timer, a counter output, and the like. It includes a program memory section for storing these items, a process flag storage section for setting a flag corresponding to the process number, and storing the set flag, including a processing instruction to be executed and a transition process. Furthermore, this programmable controller has an input / output internal relay circuit (logical transfer circuit) and a control unit described below. That is, the input / output internal relay circuit (logical transfer circuit) has an area for storing the on / off states of the input / output part, in particular, has two memory areas corresponding to each output terminal, and the first memory area has an operation immediately after program execution. Remember the state of the output. Each time one scan is finished, the contents of the first storage area are transferred to the second storage area and the contents of the first storage area are released. The control unit turns on or off a flag corresponding to the process number of the process flag storage unit in accordance with reading, interpreting, and executing the above-described command, and selects a control unit corresponding to the at least one flag while obtaining sequential information from the program storage unit, and Obtain, interpret and execute the instructions contained in the corresponding control unit. Further, the control unit obtains the logical sum of the first memory area and the second memory area of the internal / output internal relay circuit, turns off the corresponding output terminal when the logic sum is 0, and turns on the corresponding output when the logic sum is 1. (Hereinafter referred to as logical transfer). By this technique, it is possible to solve the above-mentioned problems of (a)-(c).

The programmable controller according to the present invention is controlled by the process unit as described above, and at the same time, by the above-described logical transfer, as is apparent in accordance with the above-described description and the embodiments to be described later, the programming operation becomes very easy and the operation sequence The outstanding effect that the program change at the time of the change of the back was easily performed was achieved. Furthermore, the other programmable controller which concerns on this invention has the following process address memory part with respect to the programmable controller mentioned above.

This process address storage unit stores all the process numbers of the program and the address of the above-described program memory unit in which the process numbers are stored. For this reason, the programmable control unit turns on or off the flag corresponding to the process number of the process flag storage unit as it reads, interprets, and executes only one of the above-described instructions, and turns on the flag that is turned on in accordance with the stored contents of the process address storage unit. Select the corresponding control unit, obtain information only on the instructions contained in the selected control unit, interpret it, and execute it.

Therefore, the above-described programmable controller turns on or off a flag corresponding to one process number in accordance with reading, interpreting, and executing the instruction, and turns on the process number stored in the process address storage unit and the address stored in the process number. The execution speed of the programmable controller is selected by selecting a process corresponding to one flag, and reading, interpreting, and executing only the instructions included in the selected process, and not reading the instructions included in the process with the flag off. Improve significantly.

For example, if the number of instructions in the whole program is N and the number of instructions in the process of turning on the flag is n, the execution speed of the programmable controller according to the present invention is about n / N as compared with the above.

[Best form for carrying out the invention]

Next, the flow of the control process of the programmable controller according to the present invention will be described first.

The one-step process (hereinafter referred to as the unit process) in the sequence control is a controlled body to be controlled in the unit process n as shown in FIG. 2, that is, a motor and a solenoid valve constituting the controlled system. When the output signal OUT is assigned to the output signal OUT or the like, an input signal IN corresponding to the output signal OUT, i.e., a signal such as an operation switch, a limit switch, or a timer, can be obtained. Shift to unit process (m). In contrast, FIG. 3 shows a jump to the unit process m in the unit process n.

In short, the content (K) is instructed to indicate the blocking step (implementation step) at the end of the unit step (n), and if the transition condition written in the unit step (n) is satisfied, the flag corresponding to K of the fixed flag memory unit is established. On, the result is to run the unit process (K) program. As illustrated, when K = m is programmed, the process jumps to the unit process m, and when it is programmed as K = n ', the process proceeds to the unit process n'. Then, the flag corresponding to n in the process flag storage unit is turned off, and the execution of the control of the unit process n ends.

4 to 6 show a modification of the above-described transition. 4 is a case where K = m and jumps from the unit process n to the previous unit process m. 5 shows a case in which the jump from the unit process (n) to the unit process (m) is performed, and then the unit process (m ') is blocked to block the unit processes n + 1 to m + 1. FIG. 6 means that the process shifts from the unit process (n) to the unit process (m), and then executes the unit processes m to m + α sequentially, and then inserts the unit processes m to m + α.

Similarly to the transition of such jumps, branch control or parallel control, vice versa control, and judgment control are performed.

7 is a process chart in the case of making branching control or parallel control. Two types, n 'and m, are programmed as the content K indicating the next step at the end of the unit step n.

In such a case, when the transition conditions of the unit process (n) are satisfied, as described later, flags assigned to each of the unit processes (n '') and (m) of the process flag storage unit are simultaneously turned on, and Steps n 'and (m) are in parallel control (by time division control). In other words, branch control from the unit process (n) to the unit processes (n ') and (m) is performed. It is similar to the above-mentioned case that the flag allocated to the unit process n turns off at the same time as the flag of n 'and m turns on.

8 shows a step in the case of integrating the control branched as described above, and n 'is programmed together as the interruption step K of the unit steps (n) and (m). Therefore, when the respective transition conditions are satisfied in the unit steps n and m, the corresponding flag is turned on and the flag corresponding to the unit step n 'is turned on, and the process proceeds to this unit step n'. .

The above branching or integration is basically the same as that of the pump described above, but the judgment control shown next differs slightly from these. That is, as shown in FIG. 9, the process proceeds to the unit process n 'or (m) depending on whether the transition conditions in the unit process n' are established or not. Specifically, in the program of the unit process (n), the conditions for going to the unit process (n ') and the conditions for the unit process (m) are programmed, and the process proceeds to the unit process of the condition established first of both conditions. For example, when the transition condition A is satisfied (or the transition condition to the unit process n ') is established, the flag is turned on, and the flag of the unit process n is turned off. The transition to (n ') is performed, and the control of the unit process m is not executed.

As described above, in the present invention, the unit steps can be combined so that the unit steps can be implemented, the jumps including the interruptions and the insertions can be made, branched and integrated, and the selection of the unit steps can be made by judgment.

On the other hand, with respect to the operation of the controlled object, this operation can be expressed as a combination of the above-described unit processes, which is one of the reasons why the apparatus of the present invention can be easily programmed by paying attention only to the operation of the controlled object. In the programming process executed in this manner, it is not necessary to assume a relay circuit capable of realizing the operation of each unit process.

Next, a programmable controller according to an embodiment of the present invention will be described with reference to FIG.

In the figure, reference numeral 1 denotes a control unit which is composed of a microprocessor or the like, reference numeral 2 denotes a program memory unit in which the program shown in FIG. 11 is stored, and reference numeral 3 denotes an analysis and execution performed by the controller 1; It is a program counter indicating the address of the program of the program storage unit 2 to be executed. In addition, (4) is provided in each control unit of the program of the program memory unit 2, and the process flag memory unit which stores the flag which shows operation | movement and non-operation of each control unit, and code | symbol 5 are control parts 1 Is a process flag counter indicating the address at which each flag is stored when the flag of the process flag storage unit 4 is read or when the flag is changed. Reference numeral 6 denotes an input / output unit which selects an input or an output of an address designated by a program from an input / output signal, latches the output result, and inserts the input result. Denoted at 7 is an input / output internal relay circuit, and has an area for storing the on / off states of the output terminals in the input / output unit 6, and particularly has two storage areas for each output terminal.

As shown in Fig. 12A, the first storage area 71 stores the state of the output when the program is executed. As shown in FIG. 12A, when one scan is completed, the contents of the first storage area 71 are transferred to the second storage area 72 and the contents of the first storage area 71 are released.

Here, in describing the operation of the above-described programmable controller, the outline of the program shown in FIG. 11 will be described.

This program is executed by the JMP instruction at address 4 of the step instruction at address 0, the JMP instruction at 32 at the step instruction of address 5, and so on. It is a so-called process method that divides five control units from the 59 step command to the END command of 100, so-called process method divided into each control unit, and the operation is performed for each control unit. A graph (not illustrated) showing a non-operational state is provided. Furthermore, each step instruction stores the process numbers 1, 3, 10, 13 and 20 as an operand, and each JMP instruction is an operand of each control unit to be executed after this JMP instruction. Step numbers 10, 20, 13 and 3 are stored.

In order to execute the above program, when the control unit 1 is in the operating state, the program counter 3 reads the programs of the program storage unit 2 one by one by sequentially scanning the program counter 3 from 0 to 100. At this time, as the initial state of the program controller, a value corresponding to the process number (1) is set in the flag counter (5), whereby the corresponding flag of the process flag storage unit (4) is turned on and other flags are turned off. Shall be. Since the flag of the step number (1) is in an operating state, each command of the step number (1) is read out from the program storage section 2 one by one, interpreted, and executed. Then, the 4 JMJ instructions are read and analyzed. At this time, if the transition condition STR 11 is established, the flag corresponding to the process number 1 of the process flag storage unit 4 is turned off via the process flag counter 5 according to this analysis. At the same time, the flag of the process number 10 to be executed next is turned on.

Subsequently, the control unit 1 selects the process number 3... The instructions are read sequentially, but the instruction is not executed until the instruction of the process number 10 with the above flag turned on is read. At step 33 of address 33, the command is read and the command is interpreted and executed. As described above, when one scan is completed at the 100th address, as shown in Figs. 12A and 12B, logical transfer is performed by the I / O internal relay circuit 7, and the result is that the I / O unit 6 It is sent to the external terminal through the intervening.

In other words, if any process does not produce an output during one scan, it confirms the fact and then sends an off signal to the output terminal. On the contrary, an output that is warm during one scan maintains its on state. This logical transmission has a self-holding function in a normal order.

This fact makes programming very easy, as explained later.

As described above, when one scan is finished, the instruction is read again at address 1, and the process in which the flag is turned on is executed.

Next, the program operation of the programmable controller will be described. For example, the robot hand as shown in FIG. 13A can move forward, backward, raise, lower, and catch and open the tongs, and move the workpiece from point A to point B. Think about it. The operation of the robot hand at this time can be decomposed into FIGS. 13B (a)-(i).

(a) The robot hand is in the original home position. (b) to descend. (c) Hold the workpiece. (d) to rise. (e) Go forward. (f) to descend. (g) Free the work. (h) to rise. (i) Retreat and return to its original position.

When the operation of the robot hand is expressed in a flow chart, it is as shown in Fig. 13C. In order to program this, according to the present invention, a circuit design as shown in Fig. 14 is sufficient because the self-holding function is performed in accordance with the above-described logical transfer. According to the conventional ladder method, a magnetic holding circuit is required, and a circuit design as shown in FIG. 15 is required, which is very complicated. In the case of the present invention, a key is displayed in advance in the symbol of the circuit diagram of FIG. 14, so that a program can be input while keying in the order as shown in the circuit diagram. For this reason, circuit design and program input are extremely easy. In addition, there is an advantage that even if the third party sees the circuit of Fig. 14, the flow of the entire operation can be easily understood.

Here, in the process shown in FIG. 14, for example, the logical transfer in the case of transition from the second process to the third process will be described. 16A and 16B are the above-described logical transfer diagrams, in which Fig. A shows the storage areas 71 and 72 corresponding to the falling output of the second step in the I / O internal relay circuit, and Fig. B shows the third step. It is assumed that the storage areas 71a and 72a corresponding to the capture output of?

It is assumed here that only the flag corresponding to the second process is on, and the other flags are off. When the program is read in by the first scan, only the flag corresponding to the second step is turned on, so that the program of the second step is interpreted and executed. Of course, programs of other processes including the third process can also be read, but since the flags are not turned on, the programs are not executed. Therefore, as shown in the diagram (i), the area 71 is in the on state and the area 72 is in the off state in the storage area of the falling output after the completion of one scan.

On the other hand, the storage areas 71a and 72a of the capture output are turned off because this process is not performed as shown in FIG. Next, the contents of the first storage areas 71 and 71a among the storage areas of the respective outputs are transferred to the second storage areas 72 and 72b so as to logically combine the first storage area and the second storage area, respectively. This is obtained and the result is sent to the corresponding output terminal.

In other words, the on-output appears at the lowering output terminal corresponding to the second process to perform the lowering operation. The capture output terminal corresponding to the third process remains off output. Also in the next scan, in the state where only the flag of the second process is on and other flags are off, the same logical transfer is performed as shown in Fig. 16 (ii). Next, in the scanning under the state in which the flag of the second process is turned off and the flag of the third process is turned on, it operates as shown in FIG. Since the contents of the program of the second process are not executed, the first storage area 71 is in the off state, and the second storage area 72 is in the on state by the previous logical transfer.

On the other hand, since the contents of the program of the third step are executed, the first storage area 71a is in the on state and the second storage area 72a is in the off state. When the memory contents are logically transferred as in the case described above, the falling output terminal corresponding to the second process is turned off from the on state, and the capture output terminal corresponding to the third process is turned off from the off state.

Moreover, the above description is a description of the case where the process shifts from the second process to the third process. However, the case where the other processes are performed also in other processes works similarly. In addition, it is not necessary that the scan can be repeated at a constant timing.

Next, a second embodiment of the present invention will be described.

FIG. 17 is a block diagram showing the configuration thereof, and the relationship with the embodiment of FIG. 10 is that only the process address storage section 8 and the process address counter 9 are added, and the other configurations are the same. However, with addition of these elements, the function of the control part 1A also differs slightly from that of FIG. The process address gear unit 8 reads a program of the program storage unit 12 in advance by the control unit 1A and retrieves the step instruction of the program, and the process number of the step instruction and the program counter corresponding to the step instruction ( The value of 3), that is, the address stored in the step instruction, is a storage unit that is sequentially written from address 0 as shown in FIG.

As described above, the process address counter 9 has the process number and address when the control unit 1A writes the process number and address into the process address storage unit 8 and reads the process number and address. This counter shows the stored addresses. The program memory unit 2, the program counter 3, the process flag memory unit 4, the process flag counter 5, the input / output unit 6, and the input / output internal relay circuit 7 are described with reference to FIG. Same as Therefore, the operation of the programmable controller according to the present embodiment will be described in accordance with the flowchart of FIG. 19 while focusing on the difference from that of FIG. Further, it is assumed that the program shown in FIG. 11 is stored in the program storage unit 2. As shown in FIG.

(1) step 100

When the control unit 1A enters the operating state, the program counter 3 is sequentially scanned from 0 to 100, and the program of the program storage unit 2 is read out one by one, and the step instructions in the program are searched. The process number and the address in which the process number is stored are written in the step address storage unit 8.

(2) step 101-102

The control unit 1A sets 0 in the process address counter 9 (step 101), and sets the process number and address stored in the address indicated by the process address counter 9 to the process flag counter 5 and the program counter. (3) (step 102).

(3) step 103-106

The control unit 1A reads the command stored at the address indicated by the program counter 3 (step 103), and determines whether the read command is a JMP instruction (step 104). When the instruction is other than the read JMP instruction, the instruction is interpreted and executed (step 105), the program counter 3 is increased by 10,000 (step 106), and the process proceeds to step 103.

In the case of the JMP instruction, the processing advances to step 107 only when the transition condition is satisfied. When the transition condition is not satisfied, the processing advances to step 106 (step 104a).

(4) step 107-108

The control unit 1A turns off the flag corresponding to the process flag counter 5 (the process number is set) (step 107), and turns on the flag corresponding to the process number of the read JMP instruction (step 108). ).

(5) step 109-110

The control unit 1A weighs 10,000 of the process address counter 9 (step 109), and sets the process number and address stored in the address indicated by the new step address counter 9, respectively, to the process flag counter 5 and the program counter. (3) (step 110).

(6) step 111

The control unit 1A determines whether the flag corresponding to the process flag counter 5 is off or on, advances to step 109 when it is off, and advances to step 103 when it is on. Here, after execution of step 1, the flag corresponding to step 10 is turned on. Therefore, when the process addresser 9 is weighed until the step number becomes (10), the program counter 3 is set to (33) so that the program of the program storage unit 2 is commanded from addresses 5 to 32. Will not be read.

Therefore, since the programmable controller according to the present embodiment selects, reads, analyzes, and executes only the process corresponding to the flag that is turned on, the execution speed is extremely faster than that of FIG.

Claims (2)

In a programmable controller of a control method which is stored in a program storage unit and consists of a series of programs each having a process number assigned to a predetermined control unit, which is read, interpreted, and executed according to the address indicated by the program counter. : Program memory that stores several of these, including process number, logical operation and / or data operation instruction, timer, counter output, etc. in each control unit, and sets a flag for the process number. And a process flag storage unit for storing the set flag, and having an area for storing the state of the input / output unit. In particular, it has two storage areas corresponding to each output terminal, and outputs immediately after execution in the first storage area. Memorizes the output state of the terminal, and every time one scan is finished, It is an input / output internal relay circuit which releases the contents of the storage area to the second storage area and releases the contents of the first storage area. By turning the flag corresponding to the process number on or off, selecting the control unit corresponding to this flag while reading the program storage unit sequentially, interpreting and executing the command of the corresponding control unit, and ending one scan. Each time, the control unit obtains the logical sum of the first storage area and the second storage area of the input / output internal relay circuit, turns off the corresponding output terminal when the logical sum is 0, and turns on the corresponding output when the logical sum is 1. Programmable controller equipped with It is stored in the program storage unit and reads, interprets, executes, and executes a series of programs consisting of a plurality of processes each having a process number assigned to a predetermined control unit according to the address indicated by the program counter. Is a program storage unit for storing a plurality of these, including a process number, a logical operation and / or a data processing instruction, a timer, a counter output, and the like for each control unit. A process flag storage unit for setting a flag and storing the set flag, a process address storage unit for storing the above-described process number and the address of the above-described program memory unit in which the process number is stored, and an area for storing the state of the input / output unit. In particular, two memory areas corresponding to each output terminal In the first memory area, the output state of the output terminal immediately after execution is stored, and each time one scanning ends, the contents of the first memory area are transferred to the second memory area, and the first memory area is stored. As an input / output internal relay circuit for which the contents of? Are released, the flag corresponding to the step number of the above-described process flag storage unit is turned on or off in accordance with the above-described reading, analysis, and execution, and according to the storage contents of the above-described step address storage unit, By selecting the control unit corresponding to the flag which is turned on, only the instruction included in the selected control unit is read, interpreted, and executed, and at the end of each scan, the first memory area of the internal relay circuit A program equipped with a control unit that obtains the logical sum of the second storage area, turns off the corresponding output terminal when the logical sum is 0, and turns on the corresponding output terminal when the logical sum is 1. Rammer Controller.

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