JPS62123503A - Bit arithmetic circuit for sequencer - Google Patents

Abstract

PURPOSE:To obtain a bit arithmetic circuit of a sequence with which the instruction executing time is reduced by attaining such a hardware constitution that detects and sets bits by the 3-bit information and also can execute an arithmetic processing instruction. CONSTITUTION:A 1-byte register 1 is enabled in a chip with the 1-byte/8-contact point data sent via a data bus 7 and also stores it at the time of input of the write signal WR. For an EPROM2, a terminal A12 and the data on 8 contacts supplied to terminals A0-A7 are delivered as they are through terminals D0-D7. While the data selected by the 3-bit information supplied to terminals A8-A10 are delivered through terminals D0-D7 when an arithmetic instruction is given since the terminal A12 is set at H together with one of light contact points A0-A7 designated. The data selectors 3 and 4 stores a single contact point extracted out of the 3-bit information delivered from the EPROM2 and applies the logic arithmetic to said contact point.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a bit operation circuit for a sequencer that processes instructions using hardware.

Background technology] 1. t S T A RT , S T
A RT N OT, AND, AND NOT, O
R,ORNOT.

Conventionally, instructions such as AND STK, ORSTK, and OtJT have been processed by software.

By the way, the execution of a sequence program involves the steps of analyzing sequence commands and calculating contact data. Normally, contact data is stored as 1-byte data in units of 8 contacts, and when calculating contact data, ON/OFF of the OUT command is determined by processing 1 bit.
When detecting the state of γ and performing logical operations with the operation results of l1jf processing, processing is performed using, for example, 3-bit information stored in advance in the instruction section to determine which contact out of the 8 contact units should be processed. Must.

If this process is performed by software calculations using a microcomputer that performs parallel processing in units of bytes, the time required to detect 1 bit of information and store 1 bit of information is calculated by logical operation f\: (A N There is a problem in that it takes longer than the time required for D, OR) and affects the execution time of the entire sequencer.

In addition, when the number of steps in a sequence program exceeds 2 steps, the input/output response of the sequencer becomes difficult due to the effect of the execution processing time due to cyclic operations. Even if the equipment is expanded, the scope of abstracts will be limited.

However, since it is required to shorten the execution time in a sequencer where the number of 110 points exceeds several hundred points, it is necessary to automatically detect bits and shift bits using two sets of 3-bit information. By configuring hardware that simultaneously executes arithmetic processing instructions, the time required for software will be shortened and the efficiency of programming will be increased.

[Objective of the Invention 1 The present invention has been made in view of the above points, and its object is to provide a bit operation circuit for a sequencer that uses hardware to shorten the execution time of instruction processing. .

[Disclosure of the Invention 1] Figure 1 shows the configuration of the bit operation circuit A of this embodiment, showing the human output relationship. Then, data DO to D7 are exchanged by the data bus, port addresses PAO to PA6 are transmitted by the address bus, and write signal WR is transmitted by the control bus.

A read signal RD and a chip enable signal CEO are respectively sent. FIG. 2 shows a specific circuit of the bit operation circuit A, which is a 1-byte register that stores 1-byte 8-contact data sent via the data bus 7 when the chip is enabled and when the R transmission signal WR is input. 1 and the A12 terminal is 1. ．． ” when AO-A7
The data of the 8 contacts input to the 4 children is directly DO~D7i
E outputs data from T-, and when A124 is H'', data selected by 3-bit information input to A8 to A101 to specify which contact out of 8 contacts is selected.
PROM2 and 3 bits) 1 extracted by 45 reports
Data selectors 3 and 4 that store contacts and perform logical operations, D-type 7 lip 70 knob 5, shift reno star 6,
It consists of a demultiplexer 8, a logical date, etc.

To explain in more detail, EPROM2 has 8 bytes.
t is completed, and the A12 terminal is “■-” (0 (, J T instruction)
At this time, the 8-bit data from AO to A7i is output as is from the DOD7 terminal, and the A12 terminal is H''
(operation instruction), the input data of the Al11 child is set to the specified position by the 3-bit information of the A8 to A10 terminals that specifies which bit of the input to the AO to A7 terminals, and the input data from the Do-D7 terminals is set to the specified position. Figure 5 shows [EP
This is a drawing explaining the internal data of ROM2,
a) shows when the A12 terminal is “H” (operation instruction),
Figure (b) shows when the A12 terminal is "L" (OUT command), and when the A12 terminal is "I", A8 to A
10 The input of the All terminal is set to a predetermined terminal based on the 3-bit information of the terminal. Here E P ROM
Port address PA3 is input to A12 of 2, and A8~
Port addresses PAO-P7-2 are input to AIO. Moreover, the Q output of 7 lip 70 lip 5 is input to All. 6(a), 6(b), and 6(c) show the state of data registration in the EPROM 2. In FIG. 6(a), each address of the lower 4 bytes has A 0-A ? '4 data to input into child
The data is written as is. The same figure (b) shows the registration data of the byte in 2 of 1000 to 17FF among the upper 4, and this registration data writes NO'' to the bit selected by the 3 bits of A8 to A10. In addition, the same figure (c) shows the remaining 2 (bye) (1800~IFF'
F) registration data is shown, and this registration data is 88
~1'' is written to the bit selected by the 3 bits of AIO.

Figure 7-PJ9 is the EPROM of Figure 6(a)-(c)
70-chart of the data registration method for 2 is shown, and in the figure, the address of EPROM 2 is shown, j is the value of Kawanta, i is data, α, vinegar is bit, CALI,
(i, ri, CALL(i, m>) indicates a subroutine that sets the e or logical bit of data i to 0'' or (sat) to 1, respectively.

Then, treat it as a part of the I10 boat and set the chip enable signal CEO to "L" as a boat selection signal from the micro combinator to enable each circuit element,
Next, send the data of the 8 contacts of the "c1 byte" together with the WR multiplied signal to the bit operation circuit A and store the above data in register 1. Next, set the instruction to be used in the sequencer in the port address and send the RD iK number. One byte of data will be output.Here, the instruction ORN.

T,ANDNOT,OR,,AND,5TART N
OT, '5TART, ORSKT, AND STK.

In the embodiment, the relationship between OUT and port addresses PAO to PA6 is set as shown in FIG. The instruction data for these 9 instructions consists of 3-byte instructions as shown in Figure @4, and the instruction part consists of a 4-bit port address that makes up the instruction code and a 3-bit port address that makes up the bit select information. Become.

Now, when executing the OUT instruction, the port address PA3
Since CE 1 (No. 8 is not generated, the demultiplexer 8 data selectors 3 and 41 are not enabled, and the 7 lip 70 knob 5 is in the set state, the 7 lip 70 Output Q of knob 5 is EPROM2
input to the Al14 child, and its output Ql: the corresponding A8~
AIO 3 and y) information (port address PAO-PA
The data selected in step 2) is read from the EPROM 2 and sent over the data bus 7.

On the other hand, when the logic operation g (including the S T A RT instruction) is executed, the port address PA3 is L'', so the chip enable signal CE1 is input to the data selectors 3 and 4 and enabled. A?i
The data of the 8 contacts input to the child is directly transferred to the data bus 7.
will be sent via. The data is also input to the data selector 3, and the port address P A O-P
A 1 bit selected in the 3 bit official bulletin of A2,
On/off information of the a and b contacts of the ±91 contacts 7α is output from the Y and Y terminals of the data select 3. And these outputs are AND dates 9, 10 and OR gate 11
, 12, and D4 of the data selector 4.
, D5 respectively. Of these, the input signals input to AND date 9゜10 and OR date) 11 and 12 are ANDed and ANDed respectively with the Q output of ring 70 and knob 5.
Logical operations of NOT, OR, and ORNOT are performed, and the results are input to terminals 03 to DO of the data selector 4.

Then, by uncovering the above 3-bit information of the instruction part, ORN
OT, AND NOT, OR, AND, 5TART
NOT.

5 DO from data select 4 according to each command of TART
The output of the j@child~D5 terminal is selected and set to the 7 link 707 pin 5.

, :, When executing the mrSTART instruction and the 5TART NOT instruction, contact data is set in the 7-rip 70 ring 5, and then the Q output is input to the shift register 6 and shifted to the left.

The QA and QB outputs of the shift register are AND date 13 and OR? -) 14 and logical operations are performed in each, and the date outputs are input to the D 7 r DO terminals of data select 4, respectively, and the AND
7 lip 7 for each STK command and ORSTK command
It is set to 0 to 5. Then, after setting the data for 7 rip 702 block 5, output QB is QA
It is designed to shift to the right in the direction of .

If 5TART instructions follow, for example, 5TART instructions -
The AND-OR instruction continues, and then 5 again without the OUT instruction.
TART instruction - 5 TAR if followed by AND-OR instruction
The operation results after the T instruction are registered in the shift register 6 as a stack, and in the case of AND STK and ORSTK instructions, they are shifted to the right after the operation is completed, so that the so-called FA
It has a STIN-LASTOUT structure. [Effects of the Invention j] Since the present invention is configured as described above, it is possible to perform logical operations on instruction processing simply by transferring contact data and transferring an instruction code and Zoselect information signal as a port address. As a result, the instruction execution processing time is significantly shortened compared to when processing is performed by software, and it is possible to accommodate expansion of the sequencer.

[Brief explanation of drawings]

Fig. 1 is an overall schematic configuration diagram of an embodiment of the present invention, Fig. 2 is a specific circuit diagram of the same as above, Fig. 3 is an explanatory diagram of the relationship between instructions and port addresses of the same as above, and Fig. 4 is a sequencer instruction hood of the same as above. The configuration diagram, Fig. 5 (a) and (b) is the same as above.
Explanatory diagram of internal data of PROM, Fig. 6(a)-(c)
is an explanatory diagram of the registered data of the EPROM same as above, and FIGS.
PA6 is port address, 1 is register, 2 is EPRO
M. 3.4 is a data selector, 5 is a 7 lip 70 knob 6 is a shift register, 9, 10.13 is an AND date, 11,
12.14 is an OR date.

Claims (1)

[Claims] (1) A register that stores contact data consisting of multiple bits in which information about one contact corresponds to one bit, and registers the status of each contact in advance to store the bits of the contact data and one specific contact among the contact data. A predetermined number of select information bits to be specified, an identification bit indicating whether or not it is an OUT instruction of the sequencer,
A first storage means that reads registered data based on a bit for inputting an operation result, and a first storage means that reads registered data based on a bit for inputting an operation result, and a first storage means that reads out registered data based on a bit for inputting an operation result, and a first storage means that reads registered data based on a bit for inputting an operation result, and a first storage means that reads out registered data based on a bit for inputting an operation result, and a first storage means that reads out registered data based on a bit for inputting an operation result, and a first storage means that reads registered data based on a bit that inputs an operation result. a first data selector that inputs one contact information of the bit to the logic operation means; a second data selector that selects and outputs the operation result of the logic operation means and the signal from the data selection using the select information bit; at least a second storage means that stores the signal selected by the data selector and outputs the operation result to the first storage means, and stores the sequencer instructions including the OUT instruction and the selection information bits into a plurality of bits. When the identification bit of the first storage means is set as an OUT command, the operation result replaces the input contact data with the contact data registered in advance as the data of one contact specified by the select information, and
A bit operation circuit for a sequencer, characterized in that when the identification bit is not set, registered data having the same content as the input contact data is outputted from the first storage means.