JPS6221148B2 - - Google Patents
Info
- Publication number
- JPS6221148B2 JPS6221148B2 JP57109017A JP10901782A JPS6221148B2 JP S6221148 B2 JPS6221148 B2 JP S6221148B2 JP 57109017 A JP57109017 A JP 57109017A JP 10901782 A JP10901782 A JP 10901782A JP S6221148 B2 JPS6221148 B2 JP S6221148B2
- Authority
- JP
- Japan
- Prior art keywords
- self
- diagnosis
- routine
- diagnostic
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004092 self-diagnosis Methods 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 5
- 238000003745 diagnosis Methods 0.000 description 8
- 230000004913 activation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
Description
【発明の詳細な説明】
〔発明の属する技術分野の説明〕
本発明は、情報処理装置の制御方式に関する。
特に、入出力装置における常駐型自己診断機能の
制御方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a control method for an information processing device.
In particular, the present invention relates to a control method for a resident self-diagnosis function in an input/output device.
従来、常駐型自己診断機能を有する入出力装置
は、障害発生時に上位装置からの指示により自己
診断機能を実行するが、障害内容にかかわらず全
ての自己診断機能を実行していた。
Conventionally, an input/output device having a resident self-diagnosis function executes the self-diagnosis function in response to an instruction from a host device when a failure occurs, but all self-diagnosis functions are executed regardless of the nature of the failure.
従つて、常駐型自己診断機能が豊富な入出力装
置ほど診断時間が長くなり障害発生後の自己診断
結果の報告に時間がかかる欠点がある。 Therefore, an input/output device with more resident self-diagnosis functions has the drawback that the diagnosis time is longer and it takes more time to report the self-diagnosis results after a failure occurs.
本発明は、この点を改良するもので、自己診断
時間を短縮できる入出力装置の診断制御方式を提
供することを目的とする。
The present invention improves this point, and aims to provide a diagnostic control method for input/output devices that can shorten the self-diagnosis time.
本発明は、複数の実行単位からなる常駐型自己
診断手段と、上位装置からの指定により前記自己
診断の実行単位を選択する手段と、前記選択手段
により選択された自己診断実行単位のみを順次実
行する実行制御手段と、前記選択された自己診断
終了時に診断結果を上位装置に報告する手段とを
備えたことを特徴とする。
The present invention provides a resident self-diagnosis means consisting of a plurality of execution units, a means for selecting the self-diagnosis execution unit according to a specification from a host device, and sequential execution of only the self-diagnosis execution units selected by the selection means. The present invention is characterized by comprising an execution control means for performing the self-diagnosis, and a means for reporting the diagnosis result to the host device upon completion of the selected self-diagnosis.
本発明の一実施例を図面に基づいて説明する。
図は、本発明一実施例の要部ブロツク構成図であ
る。図は自己診断ルーチンａ〜ｈが格納された固
定記憶部１と、マイクロ命令読出アドレス部２
と、このマイクロ命令読出アドレス部２で指定さ
れたマイクロ命令を実行するマイクロ命令実行部
３と、上位装置が上記自己診断ルーチンａ〜ｈに
対応するビツトa′〜h′を論理〓１〓にセツトして
指定診断ルーチン指定情報を格納する診断ルーチ
ン指定レジスタ４と、各自己診断ルーチンａ〜ｈ
の各先端マイクロ命令により各診断ルーチンａ〜
ｈに対応したビツトa″〜h″のみが論理〓１〓と
された情報が格納される診断ルーチン識別レジス
タ５と、各自己診断ルーチンａ〜ｈの各先頭マイ
クロ命令により次の自己診断ルーチンの開始アド
レスを格納する飛先アドレス格納レジスタ６と、
前記診断ルーチン指定レジスタ４の内容と前記診
断ルーチン識別レジスタ５の内容とを比較し不一
致のときには飛先アドレス格納レジスタ６の内容
を前記マイクロ命令読出アドレス部２にセツトす
る比較回路７と、前記自己診断ルーチンａ〜ｈが
実行終了時に、前記マイクロ命令実行部３から診
断結果が格納される診断結果格納レジスタ９とか
ら構成される。
An embodiment of the present invention will be described based on the drawings.
The figure is a block diagram of essential parts of an embodiment of the present invention. The figure shows a fixed storage section 1 in which self-diagnosis routines a to h are stored, and a microinstruction read address section 2.
Then, the microinstruction execution unit 3 that executes the microinstruction specified by the microinstruction read address unit 2 and the host device set the bits a' to h' corresponding to the self-diagnosis routines a to h to logic 〓1〓. A diagnostic routine designation register 4 for setting and storing designated diagnostic routine designation information, and each self-diagnosis routine a to h.
Each diagnostic routine a~
A diagnostic routine identification register 5 stores information in which only bits a'' to h'' corresponding to h are set to logic 1, and each of the first microinstructions of each self-diagnosis routine a to h is used to identify the next self-diagnosis routine. a destination address storage register 6 for storing a start address;
a comparison circuit 7 that compares the contents of the diagnostic routine designation register 4 with the contents of the diagnostic routine identification register 5 and sets the contents of the jump destination address storage register 6 to the microinstruction read address section 2 if they do not match; It is comprised of a diagnostic result storage register 9 in which the diagnostic results from the microinstruction execution section 3 are stored when the diagnostic routines a to h complete execution.
このような構成で、いま上位装置が自己診断ル
ーチンｂのみの実行を指定した場合について本発
明の特徴ある動作を説明する。 With such a configuration, the characteristic operation of the present invention will be described for the case where the host device specifies execution of only self-diagnosis routine b.
上位装置から診断すべき自己診断ルーチンｂに
対応するビツトb′のみを論理〓１〓にした情報が
送出され、これを診断ルーチン指定レジスタ４に
格納する。また、上位装置は診断起動信号Ｄを論
理〓１〓にセツトする。この診断起動信号Ｄはマ
イクロ命令読出アドレス部２の読出しアドレスを
固定記憶部１の先頭に設定するものである。 Information in which only the bit b' corresponding to the self-diagnosis routine b to be diagnosed is set to logic 1 is sent from the host device, and this information is stored in the diagnostic routine designation register 4. Further, the host device sets the diagnosis activation signal D to logic 〓1〓. This diagnostic activation signal D sets the read address of the microinstruction read address section 2 to the beginning of the fixed storage section 1.
この状態で、自己診断動作が開始されマイクロ
命令読出アドレス部２は自己診断ルーチンａの先
頭マイクロ命令を指定し、この先頭マイクロ命令
がマイクロ命令実行部３で実行される。このマイ
クロ命令は自己診断ルーチンａに対応したビツト
a″のみが論理〓１〓の情報を診断ルーチン識別レ
ジスタ５に格納するとともに飛先アドレス格納レ
ジスタ６に自己診断ルーチンｂの開始アドレスを
格納する。比較回路７で上位装置が格納した診断
ルーチン指定レジスタ４の内容と診断ルーチン識
別レジスタ５の内容が論理積される。自己診断ル
ーチンａに対応する診断ルーチン指定レジスタ４
のビツトがa′が論理〓０〓であるため論理積の結
果が論理〓０〓となる。このため、飛先アドレス
格納レジスタ６に格納されている自己診断ルーチ
ンｂの先頭アドレスがマイクロ命令読出アドレス
部２に格納される。これにより自己診断ルーチン
ｂに制御が移り、自己診断ルーチンａによる診断
は行われない。 In this state, the self-diagnosis operation is started, the microinstruction read address section 2 specifies the first microinstruction of the self-diagnosis routine a, and this first microinstruction is executed by the microinstruction execution section 3. This microinstruction is a bit corresponding to self-diagnosis routine a.
The information that only a'' is logic 1 is stored in the diagnostic routine identification register 5, and the start address of self-diagnostic routine b is stored in the destination address storage register 6. The comparison circuit 7 specifies the diagnostic routine stored by the host device. The contents of register 4 and the contents of diagnostic routine identification register 5 are ANDed.Diagnostic routine designation register 4 corresponding to self-diagnostic routine a
Since bit a' is logical 〓0〓, the result of the logical product is logical 〓0〓. Therefore, the start address of the self-diagnosis routine b stored in the destination address storage register 6 is stored in the microinstruction read address section 2. As a result, control is transferred to self-diagnosis routine b, and diagnosis by self-diagnosis routine a is not performed.
自己診断ルーチンｂでも同様に、先頭マイクロ
命令により飛先アドレス格納レジスタ６に自己診
断ルーチンＣの先頭アドレスが格納され、診断ル
ーチン識別レジスタ５には自己診断ルーチンｂに
対応したビツトb″のみが論理〓１〓にセツトさ
れる。この時、自己診断ルーチンｂに対応する診
断ルーチン指定レジスタ４のビツトb′が論理
〓１〓であるため比較回路７での論理積の結果が
論理〓１〓となる。このため、飛先アドレス格納
レジスタ６に格納された自己診断ルーチンＣの先
頭アドレスはマイクロ命令読出アドレス部２に格
納されず、自己診断ルーチンｂ内のマイクロ命令
が順次実行され診断される。 Similarly, in self-diagnosis routine b, the start address of self-diagnosis routine C is stored in the destination address storage register 6 by the first microinstruction, and only bit b'' corresponding to self-diagnosis routine b is stored in the diagnostic routine identification register 5. At this time, since bit b' of the diagnostic routine designation register 4 corresponding to self-diagnosis routine b is logic 1, the result of the AND in the comparator circuit 7 is logic 1. Therefore, the start address of the self-diagnosis routine C stored in the destination address storage register 6 is not stored in the microinstruction read address section 2, and the microinstructions in the self-diagnosis routine B are sequentially executed and diagnosed.
以下、自己診断ルーチンＣ〜ｈでは自己診断ル
ーチンａの場合と同様に、診断ルーチン指定レジ
スタ４で実行が指定されていないため比較回路７
が論理〓０〓を出力し診断が実行されず、自己診
断ルーチンｂの終了後、全ての診断が終了する。
自己診断ルーチンｂの実行結果が診断結果格納レ
ジスタ９に格納され上位装置に報告される。 Hereinafter, in self-diagnosis routines C to h, as in the case of self-diagnosis routine a, execution is not specified in the diagnosis routine designation register 4, so the comparison circuit 7
outputs logic 0 and no diagnosis is performed, and after the self-diagnosis routine b is completed, all diagnoses are completed.
The execution result of self-diagnosis routine b is stored in the diagnosis result storage register 9 and reported to the host device.
以上説明したように本発明によれば、常駐型診
断機能を上位装置から選択することを可能とする
ことにより、診断時間を著しく短縮できる効果が
ある。
As explained above, according to the present invention, by making it possible to select a resident diagnostic function from a host device, the diagnostic time can be significantly shortened.
図は本発明実施例方式の要部ブロツク構成図。
１……固定記憶部、２……マイクロ命令読出ア
ドレス部、３……マイクロ命令実行部、４……診
断ルーチン指定レジスタ、５……診断ルーチン識
別レジスタ、６……飛先アドレス格納レジスタ、
７……比較回路、９……診断結果格納レジスタ。
The figure is a block diagram of the main parts of the system according to the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Fixed storage section, 2... Microinstruction read address section, 3... Microinstruction execution section, 4... Diagnostic routine specification register, 5... Diagnostic routine identification register, 6... Destination address storage register,
7... Comparison circuit, 9... Diagnosis result storage register.
Claims (1)
された固定記憶部と、 この固定記憶部の読出アドレスを指示するマイ
クロ命令読出アドレス部と、 このアドレス部により指示された自己診断ルー
チンを実行するマイクロ命令実行部と を備え、 上記固定記憶部の内容を先頭から順次読出して
自己診断ルーチンを順次実行するように構成され
た 入出力装置の診断制御方式において、 上位装置から指定された上記自己診断ルーチン
情報を格納する回路と、 上記自己診断ルーチンの先頭マイクロ命令の実
行により次の自己診断ルーチンの開始アドレスを
格納する飛先アドレス格納回路と、 上記自己診断ルーチンの先頭マイクロ命令の実
行によりこの自己診断ルーチンを識別する情報を
格納する診断ルーチン識別回路と、 上記格納する回路と上記診断ルーチン識別回路
との内容を比較する比較回路と を備え、 上記比較回路に一致出力がないときには上記ア
ドレス部の内容を上記飛先アドレス格納回路の内
容に更新するように制御する ことを特徴とする 入出力装置の診断制御方式。[Scope of Claims] 1. A fixed storage section storing a plurality of self-diagnosis routines for each execution unit, a microinstruction read address section that specifies a read address of this fixed storage section, and a self-diagnosis routine specified by this address section. In a diagnostic control method for an input/output device, the input/output device has a microinstruction execution unit that executes a diagnostic routine, and is configured to sequentially read the contents of the fixed storage unit from the beginning and execute the self-diagnostic routine in sequence. a circuit for storing the above-mentioned self-diagnosis routine information, a destination address storage circuit for storing the start address of the next self-diagnosis routine upon execution of the first micro-instruction of the above-mentioned self-diagnosis routine, and a first micro-instruction for the above-mentioned self-diagnosis routine. A diagnostic routine identification circuit that stores information for identifying this self-diagnosis routine by execution of the diagnostic routine identification circuit, and a comparison circuit that compares the contents of the storage circuit and the diagnostic routine identification circuit, and the comparison circuit has no matching output. A diagnostic control method for an input/output device, characterized in that control is sometimes performed to update the contents of the address field to the contents of the destination address storage circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57109017A JPS58225418A (en) | 1982-06-23 | 1982-06-23 | Diagnosis controlling system of input and output device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57109017A JPS58225418A (en) | 1982-06-23 | 1982-06-23 | Diagnosis controlling system of input and output device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58225418A JPS58225418A (en) | 1983-12-27 |
| JPS6221148B2 true JPS6221148B2 (en) | 1987-05-11 |
Family
ID=14499464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57109017A Granted JPS58225418A (en) | 1982-06-23 | 1982-06-23 | Diagnosis controlling system of input and output device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58225418A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08165670A (en) * | 1994-12-14 | 1996-06-25 | Asahi Concrete Works Co Ltd | Common cable groove |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5574651A (en) * | 1978-11-30 | 1980-06-05 | Toshiba Corp | Data processor having self-diagnosis function |
| JPS5578531A (en) * | 1978-12-08 | 1980-06-13 | Mitsubishi Electric Corp | Semiconductor substrate |
-
1982
- 1982-06-23 JP JP57109017A patent/JPS58225418A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5574651A (en) * | 1978-11-30 | 1980-06-05 | Toshiba Corp | Data processor having self-diagnosis function |
| JPS5578531A (en) * | 1978-12-08 | 1980-06-13 | Mitsubishi Electric Corp | Semiconductor substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08165670A (en) * | 1994-12-14 | 1996-06-25 | Asahi Concrete Works Co Ltd | Common cable groove |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58225418A (en) | 1983-12-27 |
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