JPH01130228A - Microprogram controller - Google Patents

Abstract

PURPOSE:To process at high speed a micro-instruction accompanied with a branch by designating the address of a control storage by the contents of a branch information holding means, and simultaneously, updating the contents of the branch information holding means. CONSTITUTION:From a data which is set to a control data register 107, the least significant bit information is selected by a logical gate 103. Subsequently, address information related to an instruction processing is inputted to a micro- ROM 101, and processing corresponding to the least significant bit is started. Simultaneously, the least significant 1 bit which is in a set state in the control data register 107 is cleared, and 1 bit existing at the lowest side in the remaining bit group being in a set state is selected. After the processing to the bit being in a set stage is ended, subsequently, 1 bit being at the lowest side is selected, and the corresponding processing is started. When all bits of the register 107 are cleared, a series of instruction processings are completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and more particularly to a microprogram control device optimal for speeding up microinstructions involving branches.

[Description of prior art]

Due to factors such as the increase in the capacity of memory circuits and improvements in logic circuit design technology due to advances in integrated circuit technology, microprogramming techniques that store various control timing information in control memory have become popular in the field of microcomputers. is widely used, and detailed processing is achieved by setting microflow branching conditions and using conditional branching processing using these conditions in various places.

Among branch specifications in microprograms, there are some that specify the execution of a corresponding microprogram flow at the "1°" bit position included in 8-bit, 16-bit, etc. control data.

FIG. 5 shows an example of a microprogram flow in which branch processing is designated by conventional 8-bit control data. In this conventional example, as shown in FIG.
, C, D, E, F.

G and H, and if one bit is set, the microprogram frame corresponding to that bit is executed. That is, if bit O is 1, process A is executed, and if bit O is 1, process B is further executed.

Therefore, when the 8-bit data is 11111111, A
,B,C,D.

Execute all processing of E, F, G, H, 000ooo
For oo, A, E, C, D, E, F.

Neither G nor H processing is executed.

FIG. 7 shows a block diagram of a conventional microprogram control device for realizing this microprogram flow.

The IRI O2 is a register that holds the instruction code to be executed by this microprogram control device. Under the control of an end micro order (hereinafter referred to as END) 104, which will be described later, each time - instruction processing is completed, the next instruction code to be executed is Stored.

The selector 100 is a control device (hereinafter referred to as micro R) which will be described later.
lR10 as the read address of 101 (denoted as OM)
END 10 with the address selector that selects either the contents of 2 or the output of the micro ROM10I itself.
IRI 02 is selected at the first timing of the next instruction processing when IRI 4 becomes active, and from IRI 02 onwards, micro ROMI
Select output 01. The selector 100 moves to the next instruction process in synchronization with the timing at which the - instruction processing is completed and the END 104 becomes active, and selects the first timing IRI Q 2 again.

The microphone lffROM 101 is a control memory that holds timing information regarding processing procedures specific to each instruction.
The read address is specified by the output of micro ROMI 00, and the output of micro ROMI 01 is directly assigned to micro order 1.
11. Also, micro ROMI O1
A part of the output is again input to the selector 100 as read address information (hereinafter referred to as netast address) 106 of the micro ROMI 01.

The control data register 107 holds 8-bit control data in this conventional example and also holds the micro order 111.
It has a 1-bit right shift function by specifying . still,
In this conventional example, a micro-order specifying right shift processing is not shown.

The least significant bit of control data register 107 is connected to control gate 112 .

The control date 112 is connected to the least significant bit of the next address 106 output from the micro ROMI O1 and the branch order 113 output from the micro ROMI 01, and the output of the control gate 112 is connected to the lowest bit of the next address 106 output from the micro ROMI O1. Selector 1 as the least significant bit information
00 is entered.

FIG. 8 shows processes A, B, C, D, E, and F in the micro ROM 101 in this embodiment.

Each address assignment of G and H will be explained.

A check process for the least significant bit of the control data register 107 is set in the second address of the instruction process. Further, as shown in the figure, the address location aO where the least significant bit is 0 is shifted to the right by 1 bit of the control data register 107, and the address location a1 where the least significant bit is 1 is shifted to the right by 1 bit in the control data register 107. )
A microflow for processing A corresponding to O is set, and the address location bo whose least significant bit is 0 is set in the following order.
The control data register 10701 bit right shift processing is also performed, and the address location b whose least significant bit is 1 is
1, a microflow for processing B corresponding to bit 1 in the control data register 107 is set.

Next, the actual operation will be explained with reference to the flowchart of FIG. 5 and the blocks of FIG. 7.

However, in this conventional example, it is assumed that necessary instruction codes and 8-bit control data are stored in IRI O2 and control data register 107 in advance.

(1) To determine the execution of process A, micro ROM 10
1 outputs next address information 106aO.

At the same time, the control gate 112 is enabled in synchronization with the timing at which the branch order 113 is activated, and a process for checking whether the least significant bit of the control data is 1 or 0 is performed. 0
In this case, since 0 is logically ORed by the control gate 112, the least significant bit remains 0 and the micro ROMI
Address information aO is input to O1, and the control data is shifted to the right without executing process A. Furthermore, the bit 1 of the 8-bit control data is moved to the lowest position. 1, the control gate 112 sets the least significant bit of the netast address 106, and the micro ROM 101
Since al is input as the netast address information 106, the process moves to execution of process A. Furthermore, after executing process A, the control data is shifted to the right, and bit 1 of the 8-bit control data is moved to the lowest position.

(2) Activate branch order 113 again, (1)
Check whether the least significant bit of the right-shifted control data is 1 or 0 using the same method as above. If 0, control gate 1
Since 0 is logically ORed by 12, the least significant bit is 0.
Without executing process B, the control data is shifted to the right, and bit 2 of the 8-bit control data is moved to the lowest position. In the case of 1, the least significant bit of the netast address 106 is set by the control gate 112, so the process moves to execution of process B. After execution of process B, the control data is shifted to the right, and bit 2 of the 8-bit control data is
Move to the bottom.

By repeating the above process eight times, the 8-bit control data is determined and the necessary microprogram flow is activated.

[Problem to be Solved by the Invention 3] As explained above, in the conventional microprogram control device, execution of each corresponding process is determined by checking 8-bit control data bit by bit. That is, 8
Even if only one bit is set in the bit control data, all bits are checked one by one.
This causes a decrease in execution time.

In particular, when the processing time corresponding to each bit is relatively short, the control data check time occupies the total instruction processing, and the smaller the number of bits in the set state in the control data, the more effective the original data processing becomes. The ratio of check time to check time increases, resulting in a significant drop in overall processing efficiency.

[Object of the present invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram control device that eliminates the above-mentioned drawbacks.

[Contents of differences between the invention and the prior art] The drawback of the prior art is that the execution of each corresponding process is determined by checking 8-bit control data bit by bit. Even if the number of bits in the set state in the control data was small, it was necessary to check all bits one by one.

The present invention is characterized by stopping the judgment process for all bits and directly branching to the process corresponding to the bit position in the set state. Therefore, for example, if there are only two bits in the set state, Since processing corresponding to each bit is executed to complete a series of instruction processing, it is no longer necessary to judge all bits one by one, resulting in a significant improvement in overall execution time.

[Means for solving problems]

A microprogram control device according to the present invention relates to a microprogram control device that reads microinstructions from a control memory and processes the instructions, and includes a branch information holding means for holding branch information of a microflow, and a branch information holding means for holding branch information of a microflow. It has a branch information updating means for updating, in synchronization with a predetermined branch instruction outputted from the control memory, the read address of the control memory is designated by the content of the branch information holding means, and at the same time, the branch information is updated in synchronization with the predetermined branch instruction. A major feature is that the content of the branch information holding means is updated by the information updating means.

[Example-1] A first example based on the present invention will be described with reference to FIG.

The selector 100 selects the contents of lR102 and the micro ROMI O as the read address of the micro ROM I0I.
E is a selector for selecting either the output of E1 itself or the output of microaddress generation circuit 103, which will be described later.
In addition to selecting lR102 at the first timing of next instruction processing when ND 104 becomes active, when indirect branch specification microorder (hereinafter referred to as IDE) 105 becomes active, it selects the output of microaddress generation circuit 103, and other At the timing, the netast address 106 which is the output of the micro ROM 101 is selected.

Microaddress generation circuit 103 includes a control data register 107 and a logic gate group 108.

Since the IRI O2 and the micro ROM I0I have the same configuration as the conventional example, a detailed explanation will be omitted.

Next, referring to FIG. 2, the microaddress generation circuit 103
A more detailed configuration diagram is shown.

The microaddress generation circuit 103 includes a control data register 107 and a logic gate group 108, and clears the set least significant bit of the control data register 107 by the action of a logic gate 1080 in synchronization with the timing when the IDB 105 becomes active. Can be done.

The logic gate group 108 is a circuit for selecting the bit on the LSB side of the set bit in the control data register 107, and is constituted by an ant gate group 109.

The control data register 107 activates the same AND gate group 109 in synchronization with the timing when the IDB 105 becomes active.
The LSB of the bits set under the control of
The bit on the side is cleared.

FIG. 3 shows an example of a microprogram flow executed by the microprogram control device according to the present invention. In this embodiment, each bit of the 8-bit control data corresponds to microprogram flows A, B, C, and D, as in the conventional example.
, E, F, G, and H, but it is not a method that determines the processing flow by determining the control data bit by bit.
Branch directly to the processing flow corresponding to the bit in the set state.

Next, the operation will be explained with reference to FIG. It is assumed that the instruction code and control data are stored in the lR 102 and the control data register 107 in advance.

The logic gate 10 is generated from the control data set in the control data register 107 in the micro address generation circuit 103.
8 selects the least significant bit information in the set state. Subsequently, in synchronization with the timing at which the IDB 105 becomes active, address information related to instruction processing is input to the micro ROM 10I via the selector 100, and processing corresponding to the lowest bit in the set state is activated.

At the same time, in synchronization with the timing when the IDB 105 becomes active, the lowest 1 in the set state in the control data register 107 in the microaddress generation circuit 103
The bit is cleared, and the least significant bit among the remaining set bits becomes selected.

After completing the specified processing corresponding to the bit in the set state,
When the IDB 105 is activated again, the least significant bit in the set state in the updated control data register 107 is selected and input as a read address to the micro ROMI O1 via the selector 100. Processing corresponding to the next set bit is started.

At the same time, in synchronization with the same timing, the lowest bit that was in the set state in the control data register in the microaddress generation circuit 103 is cleared again, and the lowest bit of the remaining set bits is cleared again. The 1 bit that is selected becomes the selected state.

By repeating the above processing and clearing all bits in the control data register 103, the - series of instruction processing is completed. Furthermore, if oooooooo has been set in the control data register 103 from the beginning, the process immediately moves to the end process.

[Example-2] A block diagram of the second embodiment is shown in FIG.

Embodiment 2 has the same hardware configuration as Embodiment 1, except that the read address of the micro ROMI O1 is specified by a micro program counter (hereinafter referred to as MPC) 110.

MPCIIO is activated by lR102 or IDB105 in synchronization with the timing when END 104 becomes active.
The outputs of the microaddress generation circuits 103 are respectively selected via the selectors 100 in synchronization with the timing when the microaddress generation circuits become active, and their contents are updated. Also, END
When 104 and 105 are both inactive, MPCllo increments the contents each time the execution of one microprogram step is completed.

Since the operation of the microaddress generation circuit 103 is similar to that in Example-1, detailed explanation will be omitted.

In the second embodiment, it is not necessary to sequentially discriminate each bit for bit discrimination, and the same effect as in the first embodiment can be obtained.

〔Effect of the invention〕

As explained above, compared to the conventional microprogram control device, the microprogram control device based on the present invention does not check the 8-bit control data bit by bit to determine the execution of each corresponding process. The process branches directly to the processing corresponding to the bit being displayed. Therefore, when the number of bits in the set state is small in 8-bit control data, the determination processing time caused by the determination processing of the control bits can be reduced, making it possible to significantly shorten the total processing time.

In particular, even if the processing time corresponding to each bit is relatively short, the control data check time is not included at all, so even if the number of bits in the set state in the control data is small, the required original Only the data processing time is required, and the overall processing efficiency is greatly improved.With the addition of a small amount of hardware, processing capacity can be significantly improved, and the practical effect is extremely high.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are block diagrams showing a first embodiment of the present invention. FIG. 3 is a microprogram flow related to Example-1 of the present invention. FIG. 4 is a block diagram showing a second embodiment of the present invention. FIG. 5 shows a microprogram flow in a conventional microprogram control device. FIG. 6 is a diagram showing the correspondence between control data and actually executed processing. Figure 7 shows
FIG. 1 is a block diagram of a conventional microprogram controller. 8th
The figure shows the address assignment of a conventional micro ROM. 100...Selector, 101...Micro ROM, 102...lR1103...
...Micro address generation circuit, 104...E
ND signal, 105...IDB signal, 106...
...Next address, 107...Control data register, 108...Logic gate 109.
...and gate group, 110...MPC
1112... Control gate, 113...
branch order. Agent Patent Attorney Uchihara Sound Figure 4 Figure 5 Figure 8 Pit ml wholesale data Figure 6 Figure 7

Claims (1)

[Scope of Claim] In a microprogram control device that reads microinstructions from a control memory and performs instruction processing, there is provided a branch information holding means for holding branch information of a microflow, and a content of the branch information holding means is updated. comprising a branch information updating means, in synchronization with a predetermined branch instruction output from the control memory;
A microprogram characterized in that a read address of the control memory is specified by the contents of the branch information holding means, and further the contents of the branch information holding means are updated by the branch information updating means in synchronization with the predetermined branch instruction. Control device.