JPS58225418A - Diagnosis controlling system of input and output device - Google Patents
Diagnosis controlling system of input and output deviceInfo
- Publication number
- JPS58225418A JPS58225418A JP57109017A JP10901782A JPS58225418A JP S58225418 A JPS58225418 A JP S58225418A JP 57109017 A JP57109017 A JP 57109017A JP 10901782 A JP10901782 A JP 10901782A JP S58225418 A JPS58225418 A JP S58225418A
- Authority
- JP
- Japan
- Prior art keywords
- self
- diagnosis
- routine
- microinstruction
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
Abstract
Description
【発明の詳細な説明】 〔発明の属する技術分野の説明〕 本発明は、情報処理装置の制御方式に関する。[Detailed description of the invention] [Description of the technical field to which the invention pertains] The present invention relates to a control method for an information processing device.
特に、入出力装置における常駐型自己診断機能の制御方
式に関する。In particular, the present invention relates to a control method for a resident self-diagnosis function in an input/output device.
従来、常駐型自己診断機能を有する入出力装置は、障害
発生時に上位装置からの指示により自己診断機能を実行
するが、障害内容にかかわらず全ての自己診断機能を実
行していた。Conventionally, an input/output device having a resident self-diagnosis function executes the self-diagnosis function in response to an instruction from a host device when a failure occurs, but all self-diagnosis functions are executed regardless of the nature of the failure.
従って、常駐型自己診断機能が豊富な入出力装置はど診
断時間が長くなり障害発生後の自己診断結果の報告に時
間がかかる欠点がある。Therefore, an input/output device with abundant resident self-diagnosis functions has the drawback that it takes a long time to diagnose the device and it takes time to report the self-diagnosis results after a failure occurs.
本発明は、この点を改良するもので、自己診断時間を短
縮できる入出力装置の診断制御方式を提供することを目
的とする。The present invention improves this point, and aims to provide a diagnostic control method for input/output devices that can shorten the self-diagnosis time.
本発明は、複数の実行単位からなる常駐型自己診断手段
と、上位装置からの指定により前記自己診断の実行単位
を選択する手段と、前記選択手段により選択された自己
診断実行単位のみを順次実行する実行制御手段と、前記
選択された自己診断終了時に診断結果を上位装置に報告
する手段とを備えたことを特徴とする。The present invention provides a resident self-diagnosis means consisting of a plurality of execution units, a means for selecting the self-diagnosis execution unit according to a specification from a host device, and sequential execution of only the self-diagnosis execution units selected by the selection means. and means for reporting the diagnosis result to a host device upon completion of the selected self-diagnosis.
本発明の一実施例を図面に基づいて説明する。 An embodiment of the present invention will be described based on the drawings.
る。図は自己診断ルーチンa−hが格納された固定記憶
部1と、マイクロ命令読出アドレス部2と、このマイク
ロ命令読出アドレス部2で指定されたマイクロ命令を実
行するマイクロ命令実行部3と、上位装置が上記自己診
断ルーチンa −” hに対応するビットa′〜h′を
論理r1.にセットして指定診断ルーチン指定情報を格
納する診断ルーチン指定レジスタ4と、各自己診断ルー
チンa % hの各先頭マイクロ命令により各診断ルー
チンa % hに対応したピッ)/−h′のみが論理r
1.とされた情報が格納される診断ルーチン識別レジス
タ5と、各自己診断ルーチンa ”−hの各先頭マイク
ロ命令により次の自己診断ルーチンの開始アドレスを格
納する飛先アドレス格納レジスタ6と、前記診断ルーチ
ン指定レジスタ4の内容と前記診断ルーチン識別レジス
タ5の内容とを比較し不一致のときKli′%7 Fl
/−’=@mly Ixfi 6 f)内容′“1“
(イク四命令読出アrレス部2にセットする比較回
路7と、前記自己診断ルーチンa = hが実行終了時
に、前記マイクロ命令実行部3から診断結果が格納され
る診断結果格納レジスタ9とから構成される。Ru. The figure shows a fixed storage section 1 in which self-diagnosis routines a to h are stored, a microinstruction read address section 2, a microinstruction execution section 3 that executes a microinstruction designated by this microinstruction readout address section 2, and an upper The device sets the bits a' to h' corresponding to the self-diagnosis routines a to "h" to logic r1. to store the designated diagnostic routine designation information. By each leading microinstruction, each diagnostic routine (a)/-h' only corresponds to the logic r.
1. a diagnostic routine identification register 5 in which information about the diagnosis is stored; a destination address storage register 6 in which the start address of the next self-diagnosis routine is stored by each leading microinstruction of each self-diagnosis routine a''-h; Compare the contents of the routine designation register 4 and the contents of the diagnostic routine identification register 5, and if they do not match, Kli'%7 Fl
/-'=@mly Ixfi 6 f) Content'"1"
(from a comparison circuit 7 which is set in the instruction read address section 2, and a diagnosis result storage register 9 in which the diagnosis result from the microinstruction execution section 3 is stored when the self-diagnosis routine a = h finishes execution. configured.
このような構成で、いま上位装置が自己診断ルーチンb
のみの実行を指定した場合について本発明の特徴ある動
作を説明する。With this configuration, the host device is now running the self-diagnosis routine b.
The characteristic operation of the present invention will be described in the case where only execution of the following is specified.
上位装置から診断すべき自己診断ルーチンbに対応する
ビットb′のみを論理r1−にした情報が送出され、こ
れを診断ルーチン指定レジスフ4に〜格納する。また、
上位装置は診断起動信号pを論理!i”1.にセットす
る。この診断起動信号11マイクロ命令読出アドレス部
2の読出しアドレスを固定記憶部1の先頭に設定するも
のである。Information in which only the bit b' corresponding to the self-diagnosis routine b to be diagnosed is set to logic r1- is sent from the host device, and this information is stored in the diagnostic routine designation register 4. Also,
The host device uses the diagnostic activation signal p as logic! The read address of the microinstruction read address section 2 of this diagnostic activation signal 11 is set at the beginning of the fixed storage section 1.
この状態で、自己診断動作が開始されマイクロ命令読出
アドレス部2は自己診断ルーチンaの先頭マイクロ命令
を指定し、この先頭マイクロ命令がマイクロ命令実行部
3で実行される。このマイクロ命令は自己診断ルーチン
3に対応したビットIのみが論理fIJの情報を診断ル
ーチン識号1jレジスタ5に格納するとともに飛先アド
レス格納レジスタ6に自己診断ルーチンbの開始アドレ
スを格納する。比較回路7で上位装置が格納した診断ル
ーチン指定レジスタ4の内容と診断ルーチン識別レジス
タ5の内容が論理積される。自己診断ル−チンaに対応
する診断ルーチン指定レジスタ40ピツトa′が論理r
OJであるため論理積の結果が論理rg、となる。この
ため、飛先アドレス格納レジスタ6に格納されている自
己診断ルーチンbの先頭アドレスがマイクロ命令読出ア
ドレス音μ2に格納される。これKより自己診断ルーチ
ンbに制御が移り、自己診断ルーチンaによる診断(′
!行われない。In this state, the self-diagnosis operation is started, the microinstruction read address section 2 specifies the first microinstruction of the self-diagnosis routine a, and this first microinstruction is executed by the microinstruction execution section 3. In this microinstruction, only the bit I corresponding to the self-diagnosis routine 3 stores the information of logic fIJ in the diagnostic routine identification 1j register 5, and stores the start address of the self-diagnosis routine b in the destination address storage register 6. In the comparison circuit 7, the contents of the diagnostic routine designation register 4 and the contents of the diagnostic routine identification register 5 stored in the host device are ANDed. Diagnostic routine designation register 40 pit a' corresponding to self-diagnostic routine a is logic r.
Since it is OJ, the result of logical product is logical rg. Therefore, the start address of the self-diagnosis routine b stored in the destination address storage register 6 is stored in the microinstruction read address sound μ2. Control is transferred from K to self-diagnosis routine b, and diagnosis by self-diagnosis routine a ('
! Not done.
自己診断ルーチンbでも同様に、先頭マイクロ命令ニよ
り飛先アPレス格納レジスタ61tc 自己診断ルーチ
ンCの先頭アドレスが格納され、診断ルーチン識別レジ
スタ5には自己診断ルーチンbに対応したビット♂のみ
が論理r1Jにセットされる。この時、自己診断ルーチ
ンbに対応する診断ルーチン指定レジスタ4のピッ)
b/カー輪理r I Jであるため比較回路7での論理
積の結果力を論理rlJとなる。このため、飛先アrレ
ス格納レジスタ6に格納された自己診断ルーチンCの先
頭アドレスはマイクロ命令読出アPレス部2に格納され
ず、自己診断ルーチンb内のマイクロ命令が順次実行さ
れ診断される。Similarly, in the self-diagnosis routine b, the start address of the self-diagnosis routine C is stored in the destination address storage register 61tc from the first microinstruction 2, and only the bit ♂ corresponding to the self-diagnosis routine b is stored in the diagnosis routine identification register 5. Set to logic r1J. At this time, the diagnostic routine specification register 4 corresponding to self-diagnostic routine b)
Since the b/car cycle r I J, the resultant power of the logical product in the comparator circuit 7 becomes the logic rlJ. Therefore, the start address of the self-diagnosis routine C stored in the destination address storage register 6 is not stored in the microinstruction read address section 2, and the microinstructions in the self-diagnosis routine B are sequentially executed and diagnosed. Ru.
以下、自己診断ルーチンc −hでは自己診断ルーチン
aの場合と同様に、診断ルーチン指定レジスタ4でその
実行が指定されていないため比較回路7が論理rOJを
出力し診断が実行されず、自己診断ルーチンbの終了後
、全ての診断が終了する。自己診断ルーチンbの実行結
果が診断結果格納レジスタ9に格納され上位装置に報告
される。Hereinafter, in the self-diagnosis routine c-h, as in the case of the self-diagnosis routine a, since the execution is not specified in the diagnostic routine specification register 4, the comparison circuit 7 outputs the logic rOJ and the diagnosis is not executed, and the self-diagnosis routine is not executed. After completing routine b, all diagnostics are completed. The execution results of self-diagnosis routine b are stored in the diagnosis result storage register 9 and reported to the host device.
以上説明したように本発明によれば、常駐型診断機能を
上位装置から選択することを可能とすることにより1診
断時間を著しく短縮できる効果がある。As explained above, according to the present invention, by making it possible to select a resident diagnostic function from a host device, one diagnostic time can be significantly shortened.
図は本発明実施例方式の要部ブロック構成図。
1・・・固定記憶部、2・・・マイクi命令読出アドレ
ス部、3・・・マイクロ命令実行部、4・・・診断ルー
チアN定レジスタ、5・・・診断ルーチン識別レジスタ
、6・・・飛先アドレス格納レジスタ、7・・・比較回
路、9・・・診断結果格納レジスタ。
特許出願人 日本電気株式会社
代理人 弁理士弁 出 直 孝The figure is a block diagram of main parts of the system according to the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Fixed storage section, 2... Microphone i instruction read address section, 3... Micro instruction execution section, 4... Diagnostic routine N constant register, 5... Diagnostic routine identification register, 6... - Destination address storage register, 7... Comparison circuit, 9... Diagnosis result storage register. Patent Applicant: NEC Corporation Representative, Patent Attorney: Takashi Izunao
Claims (1)
された固定記憶部と、 この固定記憶部の読出アドレスを指示するマイクロ命令
読出アドレス部と、 このアドレス部により指示された自己診断ルーチンを実
行するマイクロ命令実行部と を備え、 上記固定記憶部の内容を先頭から順次読出して自己診断
ルーチンを順次実行するように構成された 入出力装置の診断制御方式において、 上位装置から指定された上記自己診断ルーチン情報を格
納する回路と、 上記自己診断ルーチンの先頭マイクロ命令の実行により
次の自己診断ルーチンの開始アドレスを格納する飛先ア
ドレス格納回路と、 上記自己診断ルーチンの先頭マイクロ命令の実行により
この自己診断ルーチンを識別する情報を格納する診断ル
ーチン識別回路と、 上記格納する回路と上記診断ルーチン識別回路との内容
を比較する比較回路と を備え、 上記比較回路に一致出力がないときには上記アドレス部
の内容を上記飛先アドレス格納回路の内容に更新するよ
うに制御する ことを特徴とする 入出力装置の診断制御方式。(1) A fixed memory section that stores a plurality of self-diagnosis routines for each execution unit, a microinstruction read address section that specifies the read address of this fixed memory section, and a self-diagnosis routine instructed by this address section. In a diagnostic control method for an input/output device, the input/output device has a microinstruction execution unit configured to sequentially read the contents of the fixed storage unit from the beginning and sequentially execute a self-diagnosis routine; A circuit that stores diagnostic routine information; a jump address storage circuit that stores the start address of the next self-diagnosis routine by executing the first microinstruction of the self-diagnosis routine; A diagnostic routine identification circuit that stores information for identifying a self-diagnosis routine, and a comparison circuit that compares the contents of the storage circuit and the diagnostic routine identification circuit, and when the comparison circuit does not have a matching output, the address section A diagnostic control method for an input/output device, characterized in that the content of the input/output device is controlled to be updated to the content of the destination address storage circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57109017A JPS58225418A (en) | 1982-06-23 | 1982-06-23 | Diagnosis controlling system of input and output device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57109017A JPS58225418A (en) | 1982-06-23 | 1982-06-23 | Diagnosis controlling system of input and output device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58225418A true JPS58225418A (en) | 1983-12-27 |
JPS6221148B2 JPS6221148B2 (en) | 1987-05-11 |
Family
ID=14499464
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57109017A Granted JPS58225418A (en) | 1982-06-23 | 1982-06-23 | Diagnosis controlling system of input and output device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58225418A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08165670A (en) * | 1994-12-14 | 1996-06-25 | Asahi Concrete Works Co Ltd | Common cable groove |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5574651A (en) * | 1978-11-30 | 1980-06-05 | Toshiba Corp | Data processor having self-diagnosis function |
JPS5578531A (en) * | 1978-12-08 | 1980-06-13 | Mitsubishi Electric Corp | Semiconductor substrate |
-
1982
- 1982-06-23 JP JP57109017A patent/JPS58225418A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5574651A (en) * | 1978-11-30 | 1980-06-05 | Toshiba Corp | Data processor having self-diagnosis function |
JPS5578531A (en) * | 1978-12-08 | 1980-06-13 | Mitsubishi Electric Corp | Semiconductor substrate |
Also Published As
Publication number | Publication date |
---|---|
JPS6221148B2 (en) | 1987-05-11 |
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