JPS6365983B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state history storage method, and more particularly to a state history storage method for storing history information about the internal state of an information processing device in order to trace the operation of the information processing device.

Conventionally, in this type of state history storage method,
A status information storage unit is provided in the device, and the storage unit is configured to sequentially store various internal status information of the device as input data, and when a failure occurs, the stored status information is read out and the failure is detected. It is used to investigate the cause of

Therefore, it is desirable to store as much status information as possible in order to quickly advance the cause investigation. However, in reality, it is forced to be implemented with a storage unit of limited capacity due to constraints such as price and implementation. For this reason, the following measures have been taken in the past. For example, highly important information is carefully selected from a large amount of status information and stored. Furthermore, when additional status information is required from the analysis results of the status information carefully selected as described above during the cause investigation stage when a failure occurs, the status information can be selected each time and easily used as input data. Preliminary data input should be provided in advance if possible.

However, although the above alone may provide sufficient information for relatively simple failures, when a complex failure occurs, information becomes insufficient and the above-mentioned measures become necessary. Also,
This method has the drawback that it is useful for problems that can be easily reproduced, but is powerless for problems that are poorly reproducible.

An object of the present invention is to selectively extract state information related to the function controlled by the microinstruction being executed by decoding the read data of the control memory storing the microinstruction, that is, the microinstruction word. By effectively using the limited capacity of state history storage as input data to the state history storage unit, the above disadvantages are eliminated, and a state in which sufficient history of state information can be collected even in the event of a single failure. The purpose of the present invention is to provide a history storage method.

According to the present invention, it is comprised of a plurality of arithmetic processing units that are exclusively controlled by microinstructions and a common processing unit that is commonly controlled for the plurality of arithmetic processing units, and that stores state information of these processing units. In an information processing device having a state history storage unit for sequential storage, the arithmetic processing unit is connected to a read data bus of a control storage unit storing microinstructions and is controlled by a microinstruction being executed. a state information selection circuit for selecting one set of state information from the plurality of arithmetic processing units based on arithmetic processing unit identification information output from the decoding circuit; and a state information selection circuit for selecting one set of state information from the plurality of arithmetic processing units. A state history storage system is obtained, comprising a state information storage section that stores state information from the section and the output of the state information selection circuit as input data.

Next, the present invention will be explained in detail with reference to FIG.

FIG. 1 is a block diagram of an embodiment of the present invention. This device includes a main memory section 1 for storing instructions, operands, and instruction execution results, and instructions and operands extracted from the main memory section 1, which will be described later. An instruction fetching processing unit (so-called common processing unit) 2 that supplies data to the arithmetic processing unit and stores the calculation results of the arithmetic processing unit in the main memory unit 1, and a fixed-point arithmetic processing unit that executes instructions related to fixed-point data. unit 3, floating point arithmetic processing unit 4 that executes instructions related to floating point data; variable length instruction arithmetic processing unit 5 that executes instructions related to so-called variable length data whose data length is not fixed, such as instructions related to decimal data and data editing instructions; , and four processing units that are exclusively controlled by microinstructions of the control instruction arithmetic processing unit 6 that execute branch instructions, system control instructions, etc.
Set the start microinstruction address of the instruction fetched according to the instruction specified by the instruction fetch processing section 2;
A control storage address register 8 whose address is sequentially updated according to the execution sequence of the instruction until the instruction is completed; and a control storage section 7 which stores microinstructions addressed by the control storage address register 8. , a decoding circuit 10 that decodes the read data from the control storage unit 7, that is, the microinstruction, and creates information for identifying the arithmetic processing unit that is controlled by the microinstruction currently being executed; and the four arithmetic processing units. A state information selection circuit 9 selects the state information from the control storage section 7 based on the output from the decoding circuit 10; The state information storage section 11 sequentially stores state information of the arithmetic processing section and the state information of the instruction fetch processing section 2, and a state information storage section address circuit 16 that performs address control of the state information storage section 11.

Further, the state information storage section includes a control storage address storage section 12, an arithmetic processing section identification information storage section 13, an arithmetic processing section state information storage section 14, and
It is composed of a common processing unit status information storage unit 15.

Next, the operation of the apparatus having the above configuration will be explained step by step.

First, the instruction fetch processing section 2 fetches one instruction word from the main storage section 1 via the data bus 101 and decodes the instruction. If the instruction requires operand data in the main memory 1, the data bus 101 is
The operand data is retrieved via the . When the instruction word and operand data are ready, they are supplied to the four arithmetic processing units 3 to 6 via the data bus 103, and the first microinstruction address of the microprogram that executes the instruction is generated, and the data bus 102 to the control storage address register 8. The microinstruction address is further supplied to the control storage section 7 via the data bus 104 and the corresponding microinstruction is read out onto the data bus 105. A next address section, which is part of the read microinstruction and specifies the address of the microinstruction to be executed in the next machine cycle, is set in the control storage address register 8 via the data bus 105. Other microinstruction information is similarly stored in the four arithmetic processing units 3, 4, 5, and 6.
and one of these arithmetic processing units performs a function according to the instruction of the microinstruction.

In the individual arithmetic processing units 3, 4, 5, and 6, if operand data in the main storage unit 1 is required during the execution of a specified instruction, the operand data is retrieved via the data bus 103. Instruction fetch processing unit 2
request. Furthermore, when it is necessary to store the resultant operand data in the main storage unit 1 during or at the end of instruction execution, the instruction fetching processing unit 2 is also requested to store it via the data bus 103. Instruction execution is completed by microinstruction via data bus 10.
5 to the instruction fetch processing section 2, and the instruction fetch processing section 2 proceeds to fetch the next instruction.

Next, the operation of the state history storage section will be explained. The status information storage address circuit 16 is initially set to indicate the lowest address of the status information storage unit 11 when the information processing device is reset, and from then on until a failure occurs and the function of the status history storage unit stops. The address is incremented by +1 and supplied as address information to the state information storage section 11 via the data bus 114 every machine cycle. A decoding circuit 10 for generating identification information of the arithmetic processing unit decodes the microinstruction being executed via the microinstruction word bus 105 to generate identification information on the data bus 111.
Output identification information to. The arithmetic processing unit identification information is supplied to a status information selection circuit 9, and a data bus 10 is supplied to which status information of the fixed-point arithmetic processing unit 3 is output.
6. Data bus 107 to which status information of floating point arithmetic processing unit 4 is output; variable length instruction arithmetic processing unit 5
One of the data buses 108 to which the status information of the control command arithmetic processing unit 6 is outputted and the data bus 109 to which the status information of the control instruction arithmetic processing section 6 is outputted is selected, and the result is outputted to the output data bus 112. Also,
The state information storage section 11 transfers the control storage address (microinstruction address) supplied via the data bus 104 as information for knowing the execution sequence of the microinstruction to the control storage address storage section 12 in the state information selection circuit 9. The state information of the selected arithmetic processing section is stored in the arithmetic processing section state information storage section 14, and the purpose is to easily identify which arithmetic processing section corresponds to the information stored in the arithmetic processing section state information storage section 14. Therefore, the arithmetic processing unit identification information from the decoding circuit 10 is transferred to the arithmetic processing unit identification information storage unit 13 via the data bus 111, and then transferred to the instruction fetching processing unit 2.
The status information is sequentially stored in the common processing unit status information storage unit 15 via the data bus 113 at addresses specified by the status information storage address circuit 16 for each machine cycle.

In such devices, a microinstruction word is decoded, a processing unit controlled by the currently executing microinstruction is selected, and its status information is stored in a status history storage unit. With sufficient storage capacity, a valid status history can be kept at all times.

As explained above, the present invention has the advantage that it is possible to always keep a sufficient valid state history with a limited and small storage capacity.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Main memory unit, 2... Instruction fetch processing unit, 3... Fixed point arithmetic processing unit, 4... Floating point arithmetic processing unit,
5... Variable length instruction arithmetic processing section, 6... Control instruction arithmetic processing section, 7... Control storage section, 8... Control storage address register, 9... State information selection circuit, 10... Decoding circuit, 11... State information storage section, 12 ...Control storage address storage unit, 13...Arithmetic processing unit identification information storage unit, 14...Arithmetic processing unit status information storage unit, 15...Common processing unit status information storage unit, 16...Status information storage address circuit, 101-114...Data bus.

Claims (1)

[Scope of Claims] 1 Consists of a plurality of arithmetic processing units that are exclusively controlled by microinstructions and a common processing unit that is commonly controlled for the plurality of arithmetic processing units, and the state of these processing units is In an information processing device having a state history storage unit that stores information sequentially, the operation that is connected to the read data bus of the control storage unit that stores microinstructions, and that is controlled by the microinstruction that is being executed. a decoding circuit for identifying a processing unit; a state information selection circuit for selecting one set of status information from the plurality of arithmetic processing units based on arithmetic processing unit identification information output from the decoding circuit; A state history storage system comprising: a state information storage section that stores state information from a common processing section and an output of the state information selection circuit as input data.