JPS6244663B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state history storage device that stores history information of the internal state of an information processing device for tracing the operation of the device.

Conventionally, this type of state history storage device mainly consists of a common processing section, a plurality of arithmetic processing sections, and a state information storage section that sequentially stores various internal state information of these processing sections as input data. The stored status information is read out and used to investigate the cause of a failure. Therefore, in order to quickly progress in investigating the cause, it is desirable to store as much status information as possible. However, in reality, it is forced to be implemented using a storage unit with a limited capacity due to constraints such as price and implementation.
In order to compensate for this capacity shortage, the following measures have been taken in the past. In other words, the first example is to select and store highly important information from a large amount of status information, and the second example is to select and store the most important information from a large amount of status information. Preliminary data input is provided in advance so that when additional status information is required from the analysis results of carefully selected status information, it can be easily selected as input data each time. It happened.

However, the first example alone would provide sufficient information for a relatively simple failure, but it would be insufficient when a complex failure occurs, and the second example would provide sufficient information for a failure that can be easily reproduced. Although useful, it had the drawback of being powerless against failures that were poorly reproducible.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a state history storage device that is capable of collecting a sufficient history of state information even when a failure occurs only once, using a storage unit with a limited capacity.

In order to achieve the above object, the present invention uses address information of a control memory storing a microinstruction to selectively retrieve state information related to a function controlled by a microinstruction being executed. The input data is input to the state history storage section.

According to the present invention, a common processing unit that is controlled by firmware, a plurality of arithmetic processing units that are exclusively controlled by microinstructions stored in a control memory, these plurality of arithmetic processing units, and the common processing unit In an information processing device having a state information storage section that sequentially stores state information from a section, the arithmetic processing section that is connected to the address bus of the control memory and that is controlled by a microinstruction that is being executed. an identification information creation circuit that creates arithmetic processing unit identification information for identification; and a state information storage unit that selects one set of state information from the plurality of arithmetic processing units based on the created arithmetic processing unit identification information. A state history storage device is obtained, comprising a state information selection circuit for sending the state information to the state information storage section, and means for inputting the created arithmetic processing unit identification information to the state information storage section.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a state history storage device according to an embodiment of the present invention. The information processing device shown in FIG. 1 includes a main memory 1 that stores instruction words, operands, and instruction execution results, and a main memory 1 that extracts instruction words and operands from the main memory and supplies them to an arithmetic processing section to be described later. an instruction retrieval processing section (so-called common processing section, and this name will be used hereafter) 2 which stores the calculation results in the main memory 1; A fixed-point arithmetic processing unit 3 that executes instructions related to decimal point data, a floating-point arithmetic processing unit 4 that executes instructions related to floating-point data, and instructions related to so-called variable length data whose data length is not fixed, such as instructions related to decimal data and data editing instructions. There are four arithmetic processing units: a variable-length instruction arithmetic processing unit 5 that executes instructions, and a control instruction arithmetic processing unit 6 that executes branch instructions, system control instructions, etc., and a start of the instruction taken out as specified by the common processing unit 2. A control storage address register 7 whose address is sequentially updated according to the execution sequence of the instruction until the instruction is completed; and an identification information creation circuit 9 that encodes the address from the control storage address register 7 and creates information for identifying the arithmetic processing unit that is controlled by the microinstruction currently being executed. , the status information from the four arithmetic processing units 3 to 6 is sent to the identification information creation circuit 9.
State information selection circuit 1 that selects based on the output from
0, a control memory address storage unit 11 that stores the address of the control storage unit 8, an arithmetic processing unit identification information storage unit 12 that stores the output of the identification information generation circuit 9, and a state information selection circuit 10. an arithmetic processing section state information storage section 13 that stores state information of the arithmetic processing sections 3 to 6; and a common processing section state information storage section 1 that sequentially stores state information of the common processing section 2;
4, and a state information storage address circuit 16 that controls the address of this state information storage.

Next, the functions and operations of the above configuration will be explained step by step.

First, the common processing unit 2 that fetches an instruction fetches an instruction word from the main memory 1 via the data bus 101 and decodes it. If the instruction requires operand data in the main memory 1, the operand data is further retrieved via the data bus 101. When the instruction word and operand data are ready, they are supplied to the four arithmetic processing units 3 to 6 via the data bus 102, and the first microinstruction address of the microprogram that executes the instruction is generated, and the data bus 103 to the control storage address register 7. The microinstruction address is further supplied to the control memory 8 via the data bus 104 and the corresponding microinstruction is read out onto the data bus 105. Among the read microinstructions, information specifying the address of the microinstruction to be executed in the next machine cycle is set in the control storage address register 7, and other microinstruction information is stored in the four arithmetic processing units 3, 4. , 5, 6. Then, any one of these arithmetic processing units performs a function according to the instruction of the microinstruction.

In the individual arithmetic processing units 3, 4, 5, and 6, if further operand data in the main memory 1 is required during the execution of a specified instruction, it is retrieved via the data bus 102. Common processing unit 2
request. Furthermore, when it is necessary to store the resultant operand data in the main memory 1 during or at the end of instruction execution, the common processing unit 2 is also requested to store it via the data bus 102. The completion of execution of the instruction is reported to the common processing unit 2 via the data bus 102 by the microinstruction, and the common processing unit 2 proceeds to fetch the next instruction.

Next, the operation of the state information storage section 15 will be explained.
The status information storage address circuit 16 is initially set to indicate the lowest address of the status information storage unit 15 when the information processing device is reset, and thereafter keeps the address until a failure occurs and the function of the status information storage unit 15 stops. is incremented by +1 and supplied as address information to the state information storage section 15 via the data bus 106 for each machine cycle. Arithmetic processing unit 3~
Identification information creation circuit 9 for creating identification information No. 6
outputs arithmetic processing unit identification information to the data bus 107 by decoding the storage address of the microinstruction being executed that is supplied via the data bus 104 . This arithmetic processing unit identification information is supplied to the status information selection circuit 10, and a data bus 108 to which status information of the fixed-point arithmetic processing unit 3 is output;
A data bus 109 to which state information of the floating point arithmetic processing unit 4 is output, a data bus 110 to which state information of the variable length instruction arithmetic processing unit 5 is output, and a data bus to which state information of the control instruction arithmetic processing unit 6 is output. Any one data path among 111 is selected,
The results are output to output data bus 112.

The state information storage unit 15 stores data on the data bus 104 as information for knowing the execution sequence of microinstructions.
The control memory address (microinstruction address) supplied via the control memory address storage unit 11
Then, the state information of the arithmetic processing section selected by the state information selection circuit 10 is stored in the arithmetic processing section state information storage section 13.
In order to easily identify which arithmetic processing unit corresponds to the information stored in the arithmetic processing unit status information 13, the arithmetic processing unit identification information from the identification information creation circuit 9 is transferred to the data bus 107. The common processing unit 2 is connected to the arithmetic processing unit identification information storage unit 12 via
The status information is sequentially stored in the common processing unit status information storage unit 14 via the data bus 113 at an address specified by the status information storage address circuit 16 for each machine cycle.

As explained above, the present invention uses microinstruction addresses to create arithmetic processing unit identification information, and uses this information to select the arithmetic processing unit that is being controlled by the microinstruction currently being executed, and to select its status. By storing information in the status information processing section, there is an effect that a sufficient valid status history can always be kept with a small storage capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. Explanation of symbols: 1 is main memory, 2 is common processing unit (instruction fetching processing unit), 3 is fixed-point arithmetic processing unit,
4 is a floating point arithmetic processing unit, 5 is a variable length instruction arithmetic processing unit, 6 is a control instruction arithmetic processing unit, 7 is a control storage address register, 8 is a control storage unit, 9 is an identification information creation unit, and 10 is a status information selection unit. circuit, 11 is a control memory address storage section, 12 is an arithmetic processing section identification information storage section, 13 is an arithmetic processing section state information storage section, 14
101 is a common processing unit status information storage unit; 15 is a status information storage unit; 16 is a status information storage address circuit;
. . . 113 represent data buses, respectively.

Claims (1)

[Claims] 1. A common processing unit that is controlled by firmware, a plurality of arithmetic processing units that are exclusively controlled by microinstructions stored in a control memory, and status information from these plurality of arithmetic processing units and the common processing unit. an operation for identifying the arithmetic processing unit that is connected to the address bus of the control memory and that is controlled by a microinstruction that is being executed; an identification information creation circuit that creates processing unit identification information; and a state information selection circuit that selects state information from the plurality of arithmetic processing units based on the generated arithmetic processing unit identification information and sends it to the state information storage unit. and means for inputting the generated arithmetic processing unit identification information into the state information storage unit.