JPS5810248A - Status career storage system - Google Patents

Abstract

PURPOSE:To sufficiently stock career status efficient with a limited storage capacity at all times, by selecting an operation processing section being control objective of a microinstruction executed at the succeeding instruction and storing the status information. CONSTITUTION:Discriminating information of an operation processing section being control objective mainly at the succeeding micro-instructions is set to a register 10 and the information is outputted to a data bus 111. The information is applied to a status information selection circuit 9. One data bus is selected out of a data bus 106 to which status information of a fixed decimal point operation processing section 3 is outputted, a data bus 107 to which the status information of a floating decimal point operation processing section 4 is outputted, a data bus 108 to which the status information of a variable length instruction operation processing section 5 is outputted, and a data bus 109 to which the status information of a control instruction operation processing section 6 is outputted. The result is outputted to an output data bus 112 and stored in a storage section 14.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state history storage system, and more particularly to a state history storage system VC for storing history information about the internal state of an information processing apparatus in order to trace its operation.

Conventionally, one set of υ state information is used in the method.

A status g1'# information storage section is provided in the device, and the storage section is configured to sequentially store various internal status information of the device as manual data, and outputs one set of the stored status information when a failure occurs. This is used to investigate the cause of failures.

Therefore, in order to speed up the investigation into the cause, it is desirable to record as many status 1 official gazettes as possible.

However, in reality, due to constraints such as price and implementation, it is forced to be implemented with a limited number of storage units. For this reason (7), the following measures have been taken in the past. If you click■
To select and store highly important information from a large amount of status information. (2) Furthermore, in the stage of investigating the cause of a failure, follow the results of the analysis of the status information carefully selected by
[Preliminary data input is provided so that when the status information of 1 is required, it is possible to select the status information each time and use it as input data easily.

[7 However, AIJNd Q,') alone would provide a light amount of information if it was a relatively simple failure, but when a complex failure occurs, VC
There is a lack of information, and the method described in (2) above is required. Also, ■
This method deals with failures that can be easily reproduced.
Although C was useful enough, it had a drawback that made it powerless against iC, which is a poor man's disability.

An object of the present invention is to selectively collect status IH information related to a function targeted by a series of microinstructions to be executed on the flill side 1 by using a microinstruction. By making effective use of the limited capacity of the status history memory IC, we have eliminated the drawback described in item 1 and created a status information history memory system that can collect the history of status information in the form of light even in the event of a single failure. Our goal is to provide the following.

According to the present invention, a plurality of arithmetic processing units are exclusively controlled by microinstructions, and a common processing unit is commonly controlled for the plurality of arithmetic processing units. In an information processing device that has a state history storage unit that stores sequentially, the arithmetic processing unit is connected to a read data bus of a control storage unit that stores microinstructions, and is updatable by microinstructions. a register that holds selection information; a state information selection circuit that selects all one set of state information from the plurality of arithmetic processing units based on the arithmetic processing unit selection information output from the register; A state history storage system is obtained that includes state information and a state information storage circuit that stores the state information as output data of the state information selection circuit.

Next, the present invention will be explained in detail with reference to the first cap.

FIG. 1 is a block diagram of an embodiment of the present invention, and this device includes a main memory section l for storing instruction words, operands, and instruction execution results, and an operation for extracting instruction words and operands from the main memory section l, which will be described later. an instruction extraction processing section (so-called common processing section) 2 that supplies the processing results to the processing section 1 and stores the operation results of the arithmetic processing section in the main memory; and a fixed-point calculation section that executes all instructions related to fixed-point data. Processing section 3%
Floating point arithmetic processor I8i unit that executes instructions related to floating point data 4. IjT variable length instruction arithmetic processor fI that executes all instructions related to decimal data and data editing commands, so-called variable length data whose data length is not fixed
There are four processes that are exclusively controlled by micro-instructions of the control instruction arithmetic processing section 6 that executes the control instruction calculation processing section 6 that executes branch instructions, system control instructions, etc. l! Department and.

The start microinstruction address of the instruction fetched according to the instruction specified by the instruction extraction processing section 2 is set.

Thereafter, a side slant storage address register 8 whose address is sequentially updated according to the execution sequence of the instruction until the instruction is completed; and an open side 1 storage section 7 that stores microinstructions addressed by the control storage address register 8. , a register whose contents are updated by a microinstruction read from the control memory bar li7, and in which a series of microinstructions executed after this updated microinstruction mainly selects the arithmetic processing unit targeted by the open side 1. a register lO that holds information for the above-mentioned four arithmetic processing units, a state information selection circuit 9 that selects the status 1 acknowledgment from the four arithmetic processing units according to the output from the register lO, and an address assignment of the AiJ control storage unit 7; a state information storage unit 11 that sequentially stores the output of the register 10, the state information of the arithmetic processing unit selected by the state information selection circuit 9, and the state information of the instruction collection processing unit 2; and a state information storage unit address circuit 16 that performs address control 1141 of the storage unit 11.

Further, the wandering information storage section includes a control storage address storage section 12, an arithmetic processing unit identification information storage section 13, and a control storage address storage section 13, respectively. It is composed of an arithmetic processing section, a state information storage section 14%, and a common processing section state information storage section 15.

Next, the operation of the apparatus having the above configuration will be explained step by step. First, the instruction collection processing section 2 retrieves one instruction word from the main storage section 1 via the data bus 6-101 and converts the instruction to y! (,) If the instruction requires operand data in the main memory l, the operand data is further retrieved via the data bus 101. When the instruction word and operand data are prepared, they are transferred to the data bus 103. It supplies the four arithmetic processing units 3 to 6 via the data bus 102, generates the first micro-program address of the microprogram that executes the instruction, and sets it in the control-11d self-memory address register 8 via the data bus 102. The microinstruction address is further transferred to the index 1 memory h1 via the data bus 104.
~7, the corresponding microinstructions are sent to the data bus 10.
Read out to 5. Next address f'AB data bus 10 that specifies the address of a microinstruction that is part of the read microinstruction and will be executed in the next machine cycle.
5 is set in the control storage address register 8. Similarly, the other microinstruction information of No. 7 is stored in the four arithmetic operations T! One part 3, 4, 5, 6 VC is transmitted, and any one of these arithmetic processing units performs the function according to the instruction of the microinstruction.

In the individual threshold processing units 3, 4, 5, and 6, when further operand data in the main memory unit 1 is required during the execution of a specified instruction, one data bus 103fr:
Kinrei Collection Collection 8! Request to Department 2. “Also, when it is necessary to store the resulting operand data in the main memory unit 1 during or at the end of instruction execution, the instruction collection processing unit 2 is requested to store it via the data bus 103. The completion of execution is reported to the instruction fetch processing unit 2 VC via the data bus 105 by the microinstruction.
The instruction fetching processing section 2 proceeds to fetching the next instruction.

Next, the operation of the VC1 state history storage section will be explained. The status information storage address circuit 16 is initially set to indicate the lowest F address of the status information storage unit 11 when the information processing device is reset, and from then on until a failure occurs and the function of the status history storage unit stops. , the address is incremented by +1 and is supplied as address information to the state information storage section 11 via the data bus 1i4i every machine cycle. The register 10 holding the ljt arithmetic processing identification information is set with the identification information of the arithmetic processing unit via the data bus 105, and the register 10 holds the processing identification information.
The identification information is output to 1. The arithmetic processing unit identification information is supplied to the status information selection circuit 9, and the fixed-point arithmetic processing unit 3
A data bus 106 to which status information of the floating point arithmetic processing unit 4 is outputted, and a data bus 107 to which status information of the floating point arithmetic processing unit 4 is outputted.
, one of the data buses 108 to which the status information of the machi-hen-length command calculation unit 11 5 is output and the data bus 109 to which the status information of the control command calculation unit 6 is output is selected, and the result is output data. It is output to bus 112.

The state information storage unit 11 also transfers a control memory address (microinstruction address) supplied via the data bus 104 to the control memory address storage unit 12 and the state information selection circuit 9 as information for knowing the execution sequence of the microinstruction. The status information of the selected arithmetic processing unit is stored in the arithmetic processing unit status information storage unit 14, and the information stored in the arithmetic processing unit status information storage unit 14 is stored in the arithmetic processing unit 9 for easily identifying which arithmetic processing unit corresponds to the information stored in the arithmetic processing unit status information storage unit 14. - For this purpose, the state information of the preemptive instruction output processing unit 2 is transferred from the register 10 to the arithmetic processing unit identification information storage unit 13 via the data bus 111. The common processing unit state information storage 8 (5V) is sequentially stored at the address designated by the state information storage address circuit 16 for each machine cycle.

With such a device, an effective state history can be kept in the memory at all times with a limited and small amount of memory, since it is possible to store it later in the VC using a micro-instruction.

As explained above, the present invention has the advantage that it is possible to always keep a valid status history of at least 9 minutes with a limited and small storage capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment 1+11 of the present invention. l...Main storage unit, 2...Instruction fetch processing unit, 3...10-...Fixed decimal imaginary operation processing 1-1! Part 4...Floating point arithmetic processing Capital, 5...Machi variable length instruction arithmetic processing II! t41' b 6... Control fill value calculation processing section, 7...! till arrogance, 8
Sozu... Lateral leg H [Moon, is address register, 9...
. . . Status information selection circuit, I O . . . Register, 11 . . . Wide information storage section, 12 . . .
・City 1] Busy 11 H own unique address H own memory department, 13...
...Enbu-Processing Department Identification/I'H Report 1. Part i, 14.
・・・・・・Computational processing capital state 1 reward Sozu, 15...
・Common place 1:! l! ff1i status information storage unit. 16...-state "lH report 1." is the address circuit,
lot~114... Data bus.

Claims (1)

[Claims] For a plurality of arithmetic processing units exclusively controlled by microinstructions Φ11 and for these plurality of arithmetic processing units 1jJj,
i', which consists of a common processing section that is controlled by the agreement, and has a state history storage section that sequentially stores state information of these processing sections.
*In the @i processing unit, selection 1 of the ^U arithmetic processing unit that is connected to the read data bus of the control storage unit that stores microinstructions and that can be updated by microinstructions.
# A register that holds information. a state information selection circuit for selecting one set of state information from the plurality of arithmetic processing units based on arithmetic processing unit selection information output from the register; and a state information selection circuit for selecting one set of state information from the plurality of arithmetic processing units; A state history storage method comprising: a state information storage unit that stores output as input data; and r.