JPS5810247A - Status career storage system - Google Patents

Abstract

PURPOSE:To sufficiently stock effective status career with a limited storage capacity at all times, by selecting an operation processing section being a control objective with a microinstruction when a micro instruction word is decoded and storing the status information. CONSTITUTION:A decode circuit 10 decodes a microinstruction during execution applied to a microinstruction word bus 105 and outputs operation processing recognizing information to a data bus 11. The information is applied to a status information selecting circuit 9. One data bus of any of a data bus 109 outputted with the status information of a fixed decimal point operation processing section 3, a data bus 107 outputted with the status information of a floating decimal point operation processing section 4, a data bus 108 outputted with the status information of a variable length instruction operation processing section 5, and a data bus 109 outputted with the status information of a control instruction operation processing section 6 is selected. The result is outputted to an output data bus 112 and stored in a storage section 14.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state history storage method, and more particularly to a state history storage method for storing the history and IH information of the state of an information processing device in order to trace the operation of the information processing device.

Conventionally, in this method of storing persimmon status information, status information t'i[j j: is provided in the device, and the internal status information of each pond of the device is sequentially stored in the storage unit as manual data. The state information stored at the time of failure is retrieved and used to investigate the cause of the failure.

Therefore, in order to speed up the cause investigation, it is desirable to store as much status information as possible. However, in reality, it is forced to be realized with a limited 6-stitch storage section due to the limitations of heat and mounting. For this reason, the following measures have been taken in the past. For example α)
Among the many status information, we have carefully selected the information with a high degree of armoring and recorded it as enlightenment. (Furthermore, 111 (in the case of investigation of the cause of harm, we will strictly follow the above ①), and from the wf analysis results of the state information, if the state information of 1 [i] becomes necessary, -
f: ■riB l↓ 1 (select information 7 and select
C-man-Kade = Evening and Shi "IIf it: Preliminarily set up the data manpower of jlij1 in advance""<.

(〜Kaji, previous ml(]) nodo('', Hii Kōnai 1
11 If it is a pure disorder, nine molecules z h'
Miscellaneous 111111 Harm 5 to birth time V (tzu information is insufficient and 11
The 1st step of 1st grade (?) is necessarily four and y(2,.'+).

(With the force θ of the trowel, μrφ easily appears) The obstacle that can be overcome is the VC control (7th point, the light division is the current state of the iJT, [7
It had various drawbacks that made it powerless against obstacles.

OBJECTS OF THE INVENTION V1-, Microphone 1) 'dlll +1IIl ijt with commands Xν', leaked [7
Data Immediately (-) Mike 11 life 4”i Kit decoding
By doing this, the microinstruction being executed is
iIll ZJ elephant (7taru trushrn4 Itkokan) Higashi]7ta4Js i,'! 41* @k (i = selective し (1 (Zo 11 attack 7 te 4) ζ 1 - mixed) 1!) The human power data of the 61 notebook 111 ~, and the dog 1 le j of the valley ijt. Arrogant bar 1. My 14 is all 1 big) Dan'cl 4
VC, also known as Ill.
Even in the only time a failure occurs, Koyu] 4th state j self shell + 'l
★) V (there is) to provide IM history writing system for f violet 1 emotion 3 + 17 river ability 1 shaku).

According to the VC of the present invention, the performance area of the driver that is exclusively controlled by the micro-instruction and the multiple performance area ICs
;? In the information processing device that performs the following operations, the microphone is J6 Nishikio (Tani Xl'j 1/Dairu 1th1
1. A decoding circuit for identifying the threshold processing section which is connected to the 6-source data bus VC (which is illuminated and the microinstruction being executed is controlled).

The output of the decoding circuit, which is the identification information V, is used to select the state information for selecting one set of state information from the FLFJ A circuit.

n1] A state history record 1 characterized in that the state information from 14 and the output of the state information selection circuit are memorized as a human controller; The method is based on f.

Next VC1 Mokumotoaki VC and see Figure 1 ゛C Details V
C explanation.

Figure 1 9.1 (This is a block diagram of an embodiment of the invention. 6.) Order! Rj + J Belland and the result of the execution of the loan is fully settled +11; 1 is El! 1 and 11 fire memory 71
1 (), the command word and ten pela / de are collected from 111~, and the threshold calculation process 14 old ηjL7 is supplied, and the operation process 1
The front result of iji C is shown in Part 1 above. VCpi I'
4'l'r leQ fi Ill<Source 1. ! Jjif
l ((IJ) L'JI le Jl < JJ place 111! Capital) 2
and -fJL are all fixed-point data registers, including the quality and execution of fixed-point operations 1 to 1, and 3. Floating point F-Tareko J-ru F+j
Dynamic point performance room 1! l! 4. Commands related to decimal data and data editing 6W'6 etc. So-called A' where the data to be handled is not fixed: Variable length commands to execute the 'ul'i command regarding the data VC. Reiji 5. The open side 166 executes the VC branch 66 instructions and the system control surface command. ,
Micro h11 address of the start of the extracted instruction in the previous 6 [rarely issued in the 6th order 11 of part 2]
-t, , the execution sequence of the instruction until the child -r (it sequentially sets the address 4v[!till
L wholesale d self 1. The address/metameter 8 and the control bus 1 memory address register 8V. 6.First-out data from both registers and capitals 7, ie, all microinstruction decodes F~
A decoding circuit 1 generates information for identifying the arithmetic processing unit targeted by the microinstruction currently being executed.
0 and former HL, 4 Kokumai-dokoro 1. ! 4! The state information from the section is selected by the 118 power VC from the decoding circuit 10.
Address h of FtlS 7 Address of 11'l Output of decoding circuit 10 State information of the arithmetic processing unit selected by the selection circuit 9 and output processing All the state information of the storage section 2 is stored sequentially 1, and the state information storage h1 to address controls 11 addresses in the state pleasure 1 and self-memory 1-41. 1 from circuit 16.

Furthermore, the state information ffi self-storage units are each controlled by a control address storage unit 12. Threshold processing unit identification information 6 self-storage unit] 3
% performance information storage section 14, and.

Common processing unit status - “#Report 1. consists of 15 capitals.

Next, step by step the operation of placing
- Explain.

First, the instruction fetch processing section takes out one instruction word f ll from the main memory section l via the two-digit data bus 101 and decodes the instruction. If the instruction requires operand data in section I, the data bus 101 is further activated to retrieve the operand data. When the instruction word and operand data are ready, they are sent to the four arithmetic processing units 111 via the data bus 103. 3 to 6, and also generates the first microinstruction address of the microprogram that executes all the instructions, and sets it in the control storage address register 8 via the data bus 102 (r). 104 messages (-) are supplied to the control storage section 7, and the corresponding microinstructions are successively outputted from the data bus 105i'c.

The neck address part, which is -R1i of the previous microinstruction that was successively issued, and which specifies the address information of the microinstruction to be executed in the next machine cycle, is set in the control power-down address register 8 via the data bus 105. Other microinstruction information is similarly transmitted to the four arithmetic processing units 3, 4, 5.6 of iIJ, and any one of these arithmetic processing units performs a function according to the instruction VC of the microinstruction.

In the individual arithmetic processing units 3, 4, 5, and 6, when the operand data in the main memory unit 1 is required during the execution of a specified instruction, the VIN erases the data bus 103. The 11th request to the capital city 2 for processing the withdrawal of the father's money. It's Kade.
During instruction execution and at the end of execution, the resulting operand data is stored in the main memory section IV (also when it is necessary to do so.
request. The instruction execution first child is reported to the 66th instruction fetch processing unit 2 via the data bus l05 by the microinstruction.
The instruction fetching processing section 2 proceeds to fetching the next instruction.

Next, the entire operation of the state history Hita and Hashibe will be explained. The status information storage address circuit 169 is initially set to indicate the highest address of the status information 11 when the information processing device is reset, and thereafter, when a failure occurs, the status history is stored in the memory. Increment the address by +1 (7) until the city stops functioning.
, is supplied as address information to the state information storage unit 11VC via the data bus 114 for each machine cycle. Arithmetic Processing 1] A decoding circuit IO for generating identification tH information of the Ii section outputs identification information to the data bus 111 by decoding the microinstruction being executed that is supplied by the microinstruction word bus 105. The calculation process I-! li
81≦Identification information is supplied to the status information selection circuit 9V, data bus 106° to which the status information of the fixed point arithmetic processing unit 3 is outputted, and data bus 107% to which the status 1H information of the floating point arithmetic processing unit 4 is outputted. Variable length instruction operation processing immediate execution 1~
data bus 10B and fll to which status information of 5 is output.
One of the data buses 109 to which the status information of the J eJd instruction arithmetic processing unit 6 is output is selected, and the result is output to the output data path 112 . Also, status information @
The i storage unit 11 stores the control i]1 storage address (microinstruction address) interest fi supplied via the data bus 104 as information for knowing the execution sequence of microinstructions.
The state information of the processing unit selected by the state information selection circuit 9 is stored in the memory address storage unit 12, and the state information of the processing unit selected by the state information selection circuit 9 is stored in the processing unit state information storage unit 14 and the information stored in the processing unit state information storage unit 14 is stored. In order to easily identify the corresponding arithmetic processing unit Vc, the arithmetic processing unit identification information storage unit 13 is sent to the decoding circuit 10 via the arithmetic processing unit identification information total data bus 111.
Then, the state information of the instruction fetch processing section 2 is transferred to the data bus 11.
3, the state information Nt t is sequentially stored in the common processing unit state information storage unit 15 at the address Ic specified by @Abi 2 times 1!16 every -q cycle.

In such a device, when a microinstruction word is decoded, the number of microinstructions being executed at that time is 1 to 1 less.
With the answer needle, a valid status history can be kept sufficiently at all times.

As explained above, the present invention has the advantage that it is possible to always keep a sufficient valid state history with a small storage capacity limited to VC%.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. l...Main storage unit, 2...Instruction fetch processing unit, 3...Fixed-point arithmetic processing unit, 4...
・Floating point arithmetic processing +8! Miyako, 5.2...Machi change length instruction calculation processing unit Sokuto, 6...--Kenkomeisha value calculation processing unit,
7...Full memory unit, 8...Control 1111 storage address register %9...Status information selection circuit, lO...Decoding circuit, 11...
. . . Status information storage section, 12 . . . Control storage address storage f~1513 . . . Arithmetic processing unit identification information storage Eft (%) 4 . . . Arithmetic processing unit status tI
I report i self memory department, 15... both J10 processing jlj i
l (Status information record 1: capital, 16...Status IH information storage °address circuit. 101-114...Data bus.

Claims (1)

[Claims] Consisting of a plurality of arithmetic processing units that are exclusively controlled by microinstructions and a common processing unit that is commonly controlled for the plurality of arithmetic processing units, state information of these processing units is In an information processing device having a state history storage section that sequentially stores the state history information. A decoding circuit is connected to the continuous data bus of the control memory storing the microinstructions, and is used to identify the above-mentioned (^arithmetic processing t'!1! section) which is controlled by the microinstructions being executed. , a state information selection circuit for selecting one set of state information from the plurality of arithmetic processing units based on arithmetic processing unit identification information output from the decoding circuit; and a state information selection circuit for selecting one set of state information from the plurality of arithmetic processing units. A state history storage method comprising: a state information storage section that stores circuit output as input data.