JPS5810247A - Status career storage system - Google Patents
Status career storage systemInfo
- Publication number
- JPS5810247A JPS5810247A JP56108954A JP10895481A JPS5810247A JP S5810247 A JPS5810247 A JP S5810247A JP 56108954 A JP56108954 A JP 56108954A JP 10895481 A JP10895481 A JP 10895481A JP S5810247 A JPS5810247 A JP S5810247A
- Authority
- JP
- Japan
- Prior art keywords
- information
- data bus
- status information
- arithmetic processing
- operation processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は状態履歴記憶方式、特に情報処理装置の動作ト
レースの為Vこ、装置内Ml(の状態の履歴・IH報を
記憶する状態履歴記憶方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state history storage method, and more particularly to a state history storage method for storing the history and IH information of the state of an information processing device in order to trace the operation of the information processing device.
従来、この柿の状態禰ハを記憶方式に於いては、装置内
に状態情報t’i[j j:は都を設け、該記憶部に装
置の各池内部状態情報を人力データとして逐次記憶する
様Vこ構成されていて、障害発生時に記憶されている前
記状態情報を欣出すことにより障害の原因調査に使用し
ている。Conventionally, in this method of storing persimmon status information, status information t'i[j j: is provided in the device, and the internal status information of each pond of the device is sequentially stored in the storage unit as manual data. The state information stored at the time of failure is retrieved and used to investigate the cause of the failure.
従って、原因調査を速やかに進展させる為には可能な限
り多くの状態情報を記憶しておくことが望まれる。しか
し現実はl1il]烙及び実装上衿の制約から限られた
6縫の記憶部で実現することが余儀無くされる。この為
に、従来では次の様な対策が取られていた。例えばα)
多くの状態情報の中がら重装度の高い情報を厳選して記
1、悟される。(り更に111(害発生時の原因調介没
階に於いて上記■により厳顆さね、た状態情報のwf析
結果から1〔i加の状態情報が必要どなつた場合に、−
f:■riB l↓状に1(情報を選択し7て芥vJV
C人カデー=夕とシ”ることかIIf it:な様に予
jlij1のデータ人力を予め設けて」” < 。Therefore, in order to speed up the cause investigation, it is desirable to store as much status information as possible. However, in reality, it is forced to be realized with a limited 6-stitch storage section due to the limitations of heat and mounting. For this reason, the following measures have been taken in the past. For example α)
Among the many status information, we have carefully selected the information with a high degree of armoring and recorded it as enlightenment. (Furthermore, 111 (in the case of investigation of the cause of harm, we will strictly follow the above ①), and from the wf analysis results of the state information, if the state information of 1 [i] becomes necessary, -
f: ■riB l↓ 1 (select information 7 and select
C-man-Kade = Evening and Shi "IIf it: Preliminarily set up the data manpower of jlij1 in advance""<.
(〜かじ、前ml(])のノドで(」、比II佼内的1
11純障害ならば九分子z h’<報となろうがPli
雑111111害5へ生時V(tづ情報不足となり11
1工記(?)の1・段が必四とy(2,。′+た。(〜Kaji, previous ml(]) nodo('', Hii Kōnai 1
11 If it is a pure disorder, nine molecules z h'
Miscellaneous 111111 Harm 5 to birth time V (tzu information is insufficient and 11
The 1st step of 1st grade (?) is necessarily four and y(2,.'+).
(鏝の力θくでμrφ易に出現さ)ノることの出来る障
害VC関(7て目、光分役ヴつがiJT現件の之、[7
い障害に対しては無力となる様々欠点があった。(With the force θ of the trowel, μrφ easily appears) The obstacle that can be overcome is the VC control (7th point, the light division is the current state of the iJT, [7
It had various drawbacks that made it powerless against obstacles.
本発明の目的V1−、マイク1)命令を格Xν」してい
る’dlll +1IIl ijt着、はの、流出[7
データ即(−)マイク11命4”i Kitをデコー
ドrることにより、実行中のマイクロ命令が市11 f
iIll ZJ 象ど(7ているt潰rn4 Itこ関
)東]7た4Js i、’!41* @k (i=選択
的シ(1(ゾ11冒7て4]ζ1−混)1!)情61打
帳111〜の人力データとし、田(らJした谷ijtの
犬1ルj慢バー・1.己14は全イ1大)丹′clす4
Ill rることVC、Iす1−記りく点金除にし、
唯一度の障害発生に於いても光夕〕4状j己貝悄+′l
★の)f菫1情が目3+17川能な1尺)用履歴記耐方
式をIM供することV(ある。OBJECTS OF THE INVENTION V1-, Microphone 1) 'dlll +1IIl ijt with commands Xν', leaked [7
Data Immediately (-) Mike 11 life 4”i Kit decoding
By doing this, the microinstruction being executed is
iIll ZJ elephant (7taru trushrn4 Itkokan) Higashi]7ta4Js i,'! 41* @k (i = selective し (1 (Zo 11 attack 7 te 4) ζ 1 - mixed) 1!) The human power data of the 61 notebook 111 ~, and the dog 1 le j of the valley ijt. Arrogant bar 1. My 14 is all 1 big) Dan'cl 4
VC, also known as Ill.
Even in the only time a failure occurs, Koyu] 4th state j self shell + 'l
★) V (there is) to provide IM history writing system for f violet 1 emotion 3 + 17 river ability 1 shaku).
本発明VCよると、マイクロ命令により排他的に制置さ
れる掬叔の演n処浬都と、それら複数の演鼻処浬部IC
;?j して共]jII的に制御される共通処理部とか
ら成り、−それら処11旧fBの状態情報を逐次記憶す
る状態履歴d【1世都を何する情報処理装置に於いて、
マイク「J6錦オ(谷Xl’j 1/でいる匍1th1
1記1意都の6元出しデータバスVC接(光されでいて
、実行中のマイクロ命令が制御ズ・]象どじでいる前記
閾算処浬部を識別する為のデコード回路と。According to the VC of the present invention, the performance area of the driver that is exclusively controlled by the micro-instruction and the multiple performance area ICs
;? In the information processing device that performs the following operations, the microphone is J6 Nishikio (Tani Xl'j 1/Dairu 1th1
1. A decoding circuit for identifying the threshold processing section which is connected to the 6-source data bus VC (which is illuminated and the microinstruction being executed is controlled).
該デコード回路の出力である醒算処即都識別情報Vこよ
ってflfJ A已牒数の峡昇処Hip都からの状態情
報1組を選択−す−る為の状態情報選す〈回路と。The output of the decoding circuit, which is the identification information V, is used to select the state information for selecting one set of state information from the FLFJ A circuit.
n1]記共nil処叶(14からの状態情報及び前記状
態情報選択回路の出力を人カウーータとしてl己憶する
状;島逍報記16都と金塚むことを特徴とする状態履歴
記1依方式がf支トらtする。n1] A state history record 1 characterized in that the state information from 14 and the output of the state information selection circuit are memorized as a human controller; The method is based on f.
次VC1杢元明VC一ついて第1図を奈照し゛C詳細V
C説明rる。Next VC1 Mokumotoaki VC and see Figure 1 ゛C Details V
C explanation.
第1図9よ・1(発明の一実施例のブロック図で、この
摸置け6.)令!Rj+Jベランド及び陥貸実行結果全
晴納する+11;1はEl! 1と、11火り記憶71
1(]から命令語及び十ペラ/ドを収111〜で1交述
rる閾算処14旧ηjL7こ供給し、土だ、演曽処哩1
iji Cの前線結果を上記1は部I VCpi I′
4’l’r ルQ fi Ill<出処1.!Jjif
l((イJ)L’JI ルJl<JJ処111!都)2
と、−fJLぞル固定小数点データレC関−rる品令含
・実行rる固定小数点演n処胛1〜1り3.浮動小数点
F−タレこ関J−るF+jT令ケ実’tj−C1,イY
動小数点演体処1!l!都4,10進データに関する命
令及びデータ編果6W’6等扱うデータ艮が固定でない
いわゆる用A′:艮データVC関する’ul′i令を実
r−s する呵変長命令龍算処jll怜Ji 5.並び
VC分岐66令及びシステム制御面令寺を実行r゛る開
側166ベ〕I処斗jji(6のマイクロ命令V(より
排1m的lこ111す側1されZ> 4つの処理部と、
前6[稀6令11に出処哩部2の]h定に」、り取出し
た命令のスタートのマイクロh11令アドレスケセッl
−t、、以降核品餐の児−r迄該命令の実行シーケンス
に(itつで逐次アドレスが四v[される!till
L卸d己1.ハアドレスし/ジメタ8と、該制御バ1シ
憶アドレスレジスタ8Vこ 5 −
よってアドレ、スさI−シてマイクロ命令全言己1意し
ている匍」両記簿1都7と%Ail記制両記制置都7か
らの6・先出しデータ即らマイクロ命令全デコードF〜
で現在実行中のマイクロ命令が匍1呻対象としている演
算処理部を識別rる為のm報全作り出すデコード回路1
0と、前HL、 4つの剋舞処1.!4!部からの状態
情報を前記デコ−ド回路10からの118力VCよって
選択する状4♂県情報I戊1尺回蹟9と、前出1市11
浪l己1意FtlS 7のアドレスh 11’l記デコ
一ド回路10の出ツバ前記状態悄′@i選択回路9にて
選択さtした演算処理部の状態情報及び削jjL品令嘔
出処浬部2の状態情報全逐次1も納Tる状j甜情報d己
1怠1都11と、該状態悄幸1■己憶1−41に11の
アドレス制御を行なう状態情報記憶h1〜アドレス回路
16とから1戊る。Figure 1 9.1 (This is a block diagram of an embodiment of the invention. 6.) Order! Rj + J Belland and the result of the execution of the loan is fully settled +11; 1 is El! 1 and 11 fire memory 71
1 (), the command word and ten pela / de are collected from 111~, and the threshold calculation process 14 old ηjL7 is supplied, and the operation process 1
The front result of iji C is shown in Part 1 above. VCpi I'
4'l'r leQ fi Ill<Source 1. ! Jjif
l ((IJ) L'JI le Jl < JJ place 111! Capital) 2
and -fJL are all fixed-point data registers, including the quality and execution of fixed-point operations 1 to 1, and 3. Floating point F-Tareko J-ru F+j
Dynamic point performance room 1! l! 4. Commands related to decimal data and data editing 6W'6 etc. So-called A' where the data to be handled is not fixed: Variable length commands to execute the 'ul'i command regarding the data VC. Reiji 5. The open side 166 executes the VC branch 66 instructions and the system control surface command. ,
Micro h11 address of the start of the extracted instruction in the previous 6 [rarely issued in the 6th order 11 of part 2]
-t, , the execution sequence of the instruction until the child -r (it sequentially sets the address 4v[!till
L wholesale d self 1. The address/metameter 8 and the control bus 1 memory address register 8V. 6.First-out data from both registers and capitals 7, ie, all microinstruction decodes F~
A decoding circuit 1 generates information for identifying the arithmetic processing unit targeted by the microinstruction currently being executed.
0 and former HL, 4 Kokumai-dokoro 1. ! 4! The state information from the section is selected by the 118 power VC from the decoding circuit 10.
Address h of FtlS 7 Address of 11'l Output of decoding circuit 10 State information of the arithmetic processing unit selected by the selection circuit 9 and output processing All the state information of the storage section 2 is stored sequentially 1, and the state information storage h1 to address controls 11 addresses in the state pleasure 1 and self-memory 1-41. 1 from circuit 16.
更に、前記状態情報ffi己憶部は、それぞれ制到紀儂
アドレス記憶部12.閾算処哩部識別情報6己憶部]3
%演琳処哩部状態情報記憶部14、及び。Furthermore, the state information ffi self-storage units are each controlled by a control address storage unit 12. Threshold processing unit identification information 6 self-storage unit] 3
% performance information storage section 14, and.
共通処理部状態・「#報記1.は都15から構成されて
いる。Common processing unit status - “#Report 1. consists of 15 capitals.
次に、1−記構成vciる挟置の動作を順を追って6−
−
説明する。Next, step by step the operation of placing
- Explain.
先ず、命令取出処理部2けデータバス101を介して主
記憶部lより1命令語f ll出し、該命令を解読する
。該命令が主起tは部l内のオペランドデータを必要と
するならば更にデータバス101をブtして該オペラン
ドデータを取出す。命令語とオペランドデータが揃うと
、それらをデータバス103を介して前記4つの演算処
111!部3〜6に供給すると共に、該命令全実行する
マイクロプログラムの最初のマイクロ命令アドレスを発
生し、データバス102(r介して制御記憶アドレスレ
ジスタ8にセットする。該マイクロ命令アドレスは更に
データバス104ケ介(−で制岬記憶部7に供給され該
当するマイクロ命令ケデータバス105i’c続出す。First, the instruction fetch processing section takes out one instruction word f ll from the main memory section l via the two-digit data bus 101 and decodes the instruction. If the instruction requires operand data in section I, the data bus 101 is further activated to retrieve the operand data. When the instruction word and operand data are ready, they are sent to the four arithmetic processing units 111 via the data bus 103. 3 to 6, and also generates the first microinstruction address of the microprogram that executes all the instructions, and sets it in the control storage address register 8 via the data bus 102 (r). 104 messages (-) are supplied to the control storage section 7, and the corresponding microinstructions are successively outputted from the data bus 105i'c.
続出されたマイクロ昨命令の−R1iであって次ツマシ
ンサイクルで実行されるマイクロ命令のアドレス情報定
するネックヌトアドレス部はデータバス105に介して
制御制電アドレスレジスタ8にセットされる。その他の
マイクロ命令情報は同様にしてiIJ記4つの演算処理
部3,4,5.6に伝えられ、それらの演算処理部の何
れか1つが該マイクロ命令の指示VC従った機能を遂行
する。The neck address part, which is -R1i of the previous microinstruction that was successively issued, and which specifies the address information of the microinstruction to be executed in the next machine cycle, is set in the control power-down address register 8 via the data bus 105. Other microinstruction information is similarly transmitted to the four arithmetic processing units 3, 4, 5.6 of iIJ, and any one of these arithmetic processing units performs a function according to the instruction VC of the microinstruction.
個々の演算処理部3,4.5及び6に於いては指定され
た命令の実行途中で史に主記憶部1内のオペランドデー
タが必要となった場合V仁はデータバス103をブrし
ての11父出し金茄令取出処理都2に要求する。捷だ、
命令実行途中及び実行終了時に結果のオペランドデータ
を主記憶部I V(格納する必要がある場合もまた。デ
ータバス103(r介してその格納會命令収出処哩部2
に要求する。命令実行長子はマイクロ命令によりデータ
バスl 05を介して66令取出処理部2に報告され、
命令取出処理部2は次の命令の取出へと進む。In the individual arithmetic processing units 3, 4, 5, and 6, when the operand data in the main memory unit 1 is required during the execution of a specified instruction, the VIN erases the data bus 103. The 11th request to the capital city 2 for processing the withdrawal of the father's money. It's Kade.
During instruction execution and at the end of execution, the resulting operand data is stored in the main memory section IV (also when it is necessary to do so.
request. The instruction execution first child is reported to the 66th instruction fetch processing unit 2 via the data bus l05 by the microinstruction.
The instruction fetching processing section 2 proceeds to fetching the next instruction.
次に、状態履歴日田、櫨部の動作全説明する。状態情報
記憶アドレス回路169ま杢情報処哩装置のリセット時
に状態情報i由、橡都11の最上位アドレスを示す様に
初ルj設定され、以降、障害が発生して本状態履歴i己
憶都の機能が停止する迄、アドレスを+1づつ歩進(7
,各マシンサイクル毎にデータバス114を介してアド
レス情報として状態情報記憶部11VC供給する。演算
処1]Ii部の識別tH報を作り出す為のデコード回路
lOはマイクロ命令語バス105によって供給された実
行中のマイクロ命令をデコードすることによりデータバ
ス111に識別情報を出力する。該演算処I−!li
81≦識別情報は状態情報選択回路9Vこ供給され、固
定小数点演算処理部3の状態情報が出力されるデータバ
ス106゜浮動小数点演算処理部4の状態1H報が出力
されるデータバス107%if変長命令演算処即行1〜
5の状態情報が出力されるデータバス10B及びfll
J eJd 命令演算処理部6の状態情報が出力される
データバス109の何れかlデータバスが選択され結果
が出力データパス112に出力される。また、状態情@
i記憶部11はマイクロ命令の実行シーケンスを知る為
の情報としてデータバス104を介して供給された制御
i]1記憶アドレス(マイクロ命令アドレス)金利fi
ll記憶アドレス記憶部12に、状態情報選択回路9に
て選択された演算処理部の状態情報を@誹処理都状態情
報記憶部14に、演算処理部状態情報記憶部14に記憶
された情報に対応ず9−
る演算処理部が何れであるか容易Vc識別出来る目的の
為に、デコード回路10がらの演算処理部識別情報全デ
ータバス111を介して演算処理部識別情報記憶部13
に、前記命令取出処理部2の状態情報をデータバス11
3を介して共通処理部状態情報記憶部15にそれぞれ状
態情報Nt t、@アビ2フ回1!16に:より指定さ
れたアドレスIc 各−q シyサイクル毎に逐次格納
rる。Next, the entire operation of the state history Hita and Hashibe will be explained. The status information storage address circuit 169 is initially set to indicate the highest address of the status information 11 when the information processing device is reset, and thereafter, when a failure occurs, the status history is stored in the memory. Increment the address by +1 (7) until the city stops functioning.
, is supplied as address information to the state information storage unit 11VC via the data bus 114 for each machine cycle. Arithmetic Processing 1] A decoding circuit IO for generating identification tH information of the Ii section outputs identification information to the data bus 111 by decoding the microinstruction being executed that is supplied by the microinstruction word bus 105. The calculation process I-! li
81≦Identification information is supplied to the status information selection circuit 9V, data bus 106° to which the status information of the fixed point arithmetic processing unit 3 is outputted, and data bus 107% to which the status 1H information of the floating point arithmetic processing unit 4 is outputted. Variable length instruction operation processing immediate execution 1~
data bus 10B and fll to which status information of 5 is output.
One of the data buses 109 to which the status information of the J eJd instruction arithmetic processing unit 6 is output is selected, and the result is output to the output data path 112 . Also, status information @
The i storage unit 11 stores the control i]1 storage address (microinstruction address) interest fi supplied via the data bus 104 as information for knowing the execution sequence of microinstructions.
The state information of the processing unit selected by the state information selection circuit 9 is stored in the memory address storage unit 12, and the state information of the processing unit selected by the state information selection circuit 9 is stored in the processing unit state information storage unit 14 and the information stored in the processing unit state information storage unit 14 is stored. In order to easily identify the corresponding arithmetic processing unit Vc, the arithmetic processing unit identification information storage unit 13 is sent to the decoding circuit 10 via the arithmetic processing unit identification information total data bus 111.
Then, the state information of the instruction fetch processing section 2 is transferred to the data bus 11.
3, the state information Nt t is sequentially stored in the common processing unit state information storage unit 15 at the address Ic specified by @Abi 2 times 1!16 every -q cycle.
このような装置ではマイクロ命令語をデコードしその時
点で実行しているマイクロ命令が開山1対少ない記t@
答針で有効な状態履歴を常時充分に残すことが出来る。In such a device, when a microinstruction word is decoded, the number of microinstructions being executed at that time is 1 to 1 less.
With the answer needle, a valid status history can be kept sufficiently at all times.
本発明は以上説明した様VC%限られた少ない記憶容量
で有効な状態履歴を常時充分に残すことが出来るという
効果がある。As explained above, the present invention has the advantage that it is possible to always keep a sufficient valid state history with a small storage capacity limited to VC%.
第1図は本発明の一実施例を示すブロック図で−l〇−
ある。
l・・・・・・主記憶部、2・・・・・・命令取出処理
部、3・・−・・・固定小数点演算処理部、4・・・・
・・浮動小数点演算処+8!都、5・2・・・・町変長
命令演算処即都、6・・・−・・制仰命舎値算処理部、
7・・・・・・full呻記憶部、8・・・・・・制御
1111記憶アドレスンジスタ%9・・・・・・状態情
報選択回路、lO・−・・・・デコード回路、11・・
・・・・状態情報記憶部、12・・・・・・制御記憶ア
ドレス記憶f〜1513・・・・・・演算処理部識別情
報記憶Eft(%]4・・・・・・演算処理部状態tI
I報i己憶部、15・・・・・・共J10処jlj i
l(状態情報記1:は都、16・・・・・・状態IH報
記憶°アドレス回路。
101−114・・・・・・データバス。FIG. 1 is a block diagram showing one embodiment of the present invention. l...Main storage unit, 2...Instruction fetch processing unit, 3...Fixed-point arithmetic processing unit, 4...
・Floating point arithmetic processing +8! Miyako, 5.2...Machi change length instruction calculation processing unit Sokuto, 6...--Kenkomeisha value calculation processing unit,
7...Full memory unit, 8...Control 1111 storage address register %9...Status information selection circuit, lO...Decoding circuit, 11...
. . . Status information storage section, 12 . . . Control storage address storage f~1513 . . . Arithmetic processing unit identification information storage Eft (%) 4 . . . Arithmetic processing unit status tI
I report i self memory department, 15... both J10 processing jlj i
l (Status information record 1: capital, 16...Status IH information storage °address circuit. 101-114...Data bus.
Claims (1)
部と、それら複数の演算処理部に対して共通的に制御さ
れる共通処理部とから成り、それら処理部の状態情報を
逐次記憶する状態履歴iピ憶部會有する情報処理装置に
於いて。 マイクロ命令を格納している制御記憶都の続出しデータ
バスに接続されていて、実行中のマイクロ命令が制御対
象としている前記(^算処t′!1!部を識別する為の
デコード回路と、 該デコード回路の出力である演算処理部識別情報によっ
て前記複数の演算処理部からの状態情報1組を選択する
為の状態情報選択回路と。 前記共通処理部からの状態情報及び前記状態情報選択回
路の出力を入力データとして記憶する状態情報記憶部と
を含むことを特徴とする状態履歴記憶方式。[Claims] Consisting of a plurality of arithmetic processing units that are exclusively controlled by microinstructions and a common processing unit that is commonly controlled for the plurality of arithmetic processing units, state information of these processing units is In an information processing device having a state history storage section that sequentially stores the state history information. A decoding circuit is connected to the continuous data bus of the control memory storing the microinstructions, and is used to identify the above-mentioned (^arithmetic processing t'!1! section) which is controlled by the microinstructions being executed. , a state information selection circuit for selecting one set of state information from the plurality of arithmetic processing units based on arithmetic processing unit identification information output from the decoding circuit; and a state information selection circuit for selecting one set of state information from the plurality of arithmetic processing units. A state history storage method comprising: a state information storage section that stores circuit output as input data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56108954A JPS5810247A (en) | 1981-07-13 | 1981-07-13 | Status career storage system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56108954A JPS5810247A (en) | 1981-07-13 | 1981-07-13 | Status career storage system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5810247A true JPS5810247A (en) | 1983-01-20 |
JPS6365983B2 JPS6365983B2 (en) | 1988-12-19 |
Family
ID=14497859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56108954A Granted JPS5810247A (en) | 1981-07-13 | 1981-07-13 | Status career storage system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5810247A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6457346A (en) * | 1987-08-27 | 1989-03-03 | Fujitsu Ltd | Microtracing system |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10350431B2 (en) | 2011-04-28 | 2019-07-16 | Gt Medical Technologies, Inc. | Customizable radioactive carriers and loading system |
US9492683B2 (en) | 2013-03-15 | 2016-11-15 | Gammatile Llc | Dosimetrically customizable brachytherapy carriers and methods thereof in the treatment of tumors |
US9821174B1 (en) | 2015-02-06 | 2017-11-21 | Gammatile Llc | Radioactive implant planning system and placement guide system |
US10888710B1 (en) | 2016-11-29 | 2021-01-12 | Gt Medical Technologies, Inc. | Transparent loading apparatus |
US10981018B2 (en) | 2019-02-14 | 2021-04-20 | Gt Medical Technologies, Inc. | Radioactive seed loading apparatus |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5530729A (en) * | 1978-08-22 | 1980-03-04 | Nec Corp | Action career memory system for logic device |
-
1981
- 1981-07-13 JP JP56108954A patent/JPS5810247A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5530729A (en) * | 1978-08-22 | 1980-03-04 | Nec Corp | Action career memory system for logic device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6457346A (en) * | 1987-08-27 | 1989-03-03 | Fujitsu Ltd | Microtracing system |
Also Published As
Publication number | Publication date |
---|---|
JPS6365983B2 (en) | 1988-12-19 |
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