JPS60237503A - High-speed processing system of sequence controller - Google Patents

Abstract

PURPOSE:To speed up arithmetic processing by performing the memory readout operation of an ALU and the processing of bit arithmetic logic simultaneously by the processing of the sequence controller. CONSTITUTION:The ALU1 reads and writes a user program and data out of and in a memory device 3 under the control of an ALU control part 2. Further, a bit arithmetic circuit 6 performs arithmetic as to specific bits from a bit selecting circuit 5 and bits held in a bit accumulator 7 and stores the result in the accumulator 7. Further, a logical circuit 8 for OUT instructions performs logical arithmetic between bits of data selected by the ALU1 and bit data in the bit accumulator 7 when the user program read out of the memory 3 is an OUT instruction. Thus, the readout of the data memory and small arithmetic are carried out in parallel and the number of processing steps is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a control configuration improved so that logical operations (bit operations) of a sequence controller can be processed at high speed.

<Prior Art> Sequence controllers are effectively used in the automation of various industrial equipment. Recently, computer technology has been applied to programmable sequence controllers or programmable logic controllers that eliminate the drawbacks of conventional relay circuits through programs, and have been proposed and put into practical use. Process the command as follows.

+11 Read the user program from memory.

(2) Read the data memory specified by the read user program.

(3) Decipher the user program, perform the specified bit operation, and store the result in the bit accumulator (bit Ac
e).

By the way, in the conventional controller of this type, the fl+
, (21, +31 steps are processed sequentially, so +I required for arithmetic processing of one basic instruction) → (2
)→(3), and when a large number of basic instructions are sequentially computed, a problem arises in terms of speeding up the computation.

The purpose of this FIA is to speed up the above-mentioned arithmetic processing of the sequence controller, and in particular, to speed up the processing steps of fl) and (21, T3) mentioned above. The processing of (3) and (3) can be processed in parallel to speed up the calculation.
Figures (a) and (b) show the time charts.

In FIG. 1, reference numeral 1 denotes an ALU having three 16-bit ports 1, A, B, and Y, and reads and writes user programs and data under the control of an ALU control section 2.

Reference numeral 3 denotes a memory device, which includes an area 3A for storing user programs and an area 3B for storing data.

4A, 4B, 4C, and 4D are input/output control gates for the memory device 30, which control address data to the gate 4Afl memory, and further transmit control signals to the gate 4 (gate 4) to the Jj memory or to the gate 4BH memory. It controls data from memory.

5 is a bit selection circuit, which selects a specific bit of data when the data is taken out from the memory device @ 3 through the Y bus to ALUI. 0 6 is a bit selection circuit sent from the bit selection circuit 5. This is a bit arithmetic circuit that performs logical operations on bits and bits held in bit accumulator (bit Ace) 7, and the arithmetic results in this circuit 6 are stored in bit Acc7. When the user program read from the memory issues an OUT command (command to write the contents of bit Acc7 to the specified bit of the data memory), the selected bit of the data taken out to the ALUI through the Y bus is selected by the bit selection circuit 5. It is supplied through the bit Acc7 and executes a logical operation (EXOR)' with the bit data of bit Acc7.

9 is a clock pulse generator, and 7'vlO is a stack memory.

Next, the block configuration shown in FIG. 1 will be explained together with the time chart shown in FIG. 2.

First, the processing of basic instructions is as follows: (1) Read the user program from memory0(2)
Reads the data memory specified by the read user program, performs the specified bit operation, and stores the result in bi
This step executes the step of storing 0 in t Acc .

That is, φ in FIG. 2(a) is a clock signal from the clock pulse generator 9, which is supplied to the ALUI and the ALU control unit 2.

First, in cycle T1, ALU 1 reads the user program from memory device 3.
Address information is supplied to the memory device 3 via the address bus B'5 of I, and the user program area 3A is accessed.

The user program from this memory device 3 is stored in an internal register (p>) in the ALUI via the Y bus.

When this stored user program is a basic instruction, it has a bit configuration as shown in FIG. This is it.

-b is the address DMA of the data memory,
b I(1'' I□ is bit position selection information BS for data, and b, 3 to b, 5u bit operation selection information RAS.

Subsequently, at cycle time T2, the ALUI
The basic instruction stored in the internal register (p) in ob is output to address bus B, and this basic instruction ob. The 10-bit address information DMA of -b9 is supplied to the memory device 3 as an address of the data area 3B of the memory device 3. The bit selection information BS of ~b1□ is supplied to the bit selection circuit 5, and further the bit operation selection information BAlj of bI3 to b15 is supplied to the bit operation circuit 6.

And the above. -b9 address information The data read from the memory device 3 by DMA is sent to the ALU via the Y bus.
) of I's internal registers. Also, during the data read to the Y bus, a predetermined bit of the data is taken in based on the bit selection information BS held in the bit selection circuit 5, and is supplied to the next bit operation circuit 6. Bit arithmetic circuit 6 hab! The operation specified by the bit operation selection information BAS of 3 to b+5 is executed between the supplied specified bit and the bit held by bit Acc7, and the operation result is stored in ebit Acc7.

The above sequence completes one operation of the basic instruction. In this case, as is clear in FIG. 2(a), data memory reading and small operations are processed in parallel.
It can be processed by just steps (1) and (2) above.

Next, FIG. 2(b) r/'i is a time chart when the user program is an OUT instruction (an instruction to write the contents of bit Acc7 to a designated bit of the data memory) after the execution of the above basic instruction. .

That is, in the TI cycle as described above, the user program in the memory device 3 is stored in the internal register φ) of the ALUI via the Y path.

If this is an OUT command, a bus BKOUT command is output in the cycle T2, the address data of bo-b9 is supplied to the memory device 3, the bit selection information of blo"b12 is supplied to the bit selection circuit 5, and the bit selection information of blo"b12 is supplied to the bit selection circuit 5, and further ~
The b+6 bit operation selection information is supplied to the OUT instruction logic circuit 8. Then, the data 1dALU+ read out from the memory device 3 onto the Y bus is stored in the internal register (c).

In addition, the data read to the Y bus has a predetermined bit taken in based on the bit selection information held in the bit selection circuit 5, and the next OUT instruction logic circuit 8
and the calculations shown in FIG. 4 are performed.

In FIG. 4, the data has an 8-bit configuration, and when the bit selection circuit 5 specifies the third bit d' of the data, the third bit d3 and the bit B held in the bit Acc7 are If they are equal (d 3 =B ), the result is PA0'' as shown in FIG. 4(a), and in the case of d3\B, the value is "T' as shown in FIG. 4(b).

Then, the third bit d3 is calculated and latched into the OUT instruction logic 8 in an 8-bit configuration with all other bits If set to "0".

Subsequently, in the next T3 cycle, flALU+ is connected to the OUT
An exclusive OR (ExOR) operation is performed on the operation result latched in the instruction logic 8 and the data (8-bit configuration) held in the internal register (6), and this result is stored in the internal register (6). Ru.

The operation result stored in this internal register (D) is the above T
Regarding the data read from the data memory in two cycles, the bit designated by "10"b+2 of the user program is replaced with the contents of bit Acc7.

Then, in cycle T4, ALUI writes the contents of internal register D to data area 3B of memory device 3. This completes the execution of the OUT instruction.
In this case as well, as is clear from Figure 2), the memory device 3
Logic 8 for reading data memory from and OUT command
The calculations are processed in parallel, allowing for high-speed processing.

In FIGS. 2(a) and 2(b), ill is the signal of the clock pulse generator 9, (2) is the A bus of ALUI, (3) is the B bus, (4) is the Y bus, and (5) is the signal of the clock pulse generator 9. ) indicates the operating state, and (6) indicates the data held in bit Acc7, respectively.

<Effects> As described above, in the present invention, by performing ALU memory reading and bit operation logic processing in parallel in sequence controller processing, +11
(2) reading the user program from memory;
) Processing can be performed in two steps: reading data memory and performing specified bit operations, reducing the number of processing steps when processing a large number of instructions in sequence, greatly speeding up the sequence controller's calculation time and enabling high-speed processing. It has the following characteristics.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the control structure of the present invention, Figure 2 is a time chart showing the operation of the configuration in Figure 1, Figure 3 is a diagram showing the bit configuration of basic instructions, and Figure 4 is for OUT instructions. FIG. 3 is a diagram showing calculations of a logic circuit. 1: ALU, 2: ALU control section, 3: Memory device, 5: Bit selection circuit, 6: Bit operation logic circuit, 7: Bit accumulator, 8: OUT instruction logic circuit.

Claims (1)

[Claims] 1. A memory device that holds programs and data;
An ALU that reads a program instruction from the memory device and executes an operation instruction according to the instruction, an operation on the read data, etc., and a predetermined driver designated by the program instruction for the data loaded from the memory device to the ALU. a bit selection circuit; and a bit operation circuit that is supplied with a predetermined bit selected by the selection circuit and executes a logical operation instructed by the program instruction, and simultaneously reads data from the memory device to the ALtJ. A selection circuit and a bit operation circuit perform calculation processing,
1. A high-speed processing method for a sequence controller, characterized in that data read processing and bit operation processing are performed in parallel.