JPS63158608A - Quick arithmetic processing system for sequencer - Google Patents

Abstract

PURPOSE:To increase the arithmetic processing speed by providing a bit operating circuit and a bit selecting circuit to process a fundamental operation instruction and an OUT instruction at the same time. CONSTITUTION:A bit selecting circuit 4 selects one bit in case of the fundamental operation instruction and inserts a bit in case of the OUT instruction in accordance with the instruction of a bit operating circuit 5 and outputs them to a bus D. The bit operating circuit 5 takes in data on the bus D to perform bit operation in case of the fundamental operation instruction and outputs a write signal WT to a memory device 3 to write data including the operation result in a memory device 3 in case of the OUT instruction. Thus, the fundamental operation instruction and the OUT instruction pass the same processing process until operation data is latched in a latch circuit 8c. Consequently, the difference of processing time between the fundamental operation instruction and the OUT instruction is eliminated to increase the processing speed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a logic operation processor Fl! in a sequence controller. This invention relates to a high-speed arithmetic processing method for a sequencer that performs (bit arithmetic processing) at high speed.

[Background technology 1 The program processing method in a sequence controller generally employs a method in which the entire sequence control program is scanned and calculated sequentially, and the calculation results are output once per scan to control the machine. Therefore, the scan time increases in proportion to the increase in program amount. This means that the control interval becomes longer and the response to the machine becomes slower.

For this reason, efforts are generally made to speed up calculations. For example, the known example shown in Japanese Patent Application Laid-Open No. 60-237503 processes data reading and bit calculation processing in parallel, and not only performs sequential calculations by the CPU. The hardware processing of the rad calculation unit is used to increase speed. Here, there are basic operation instructions (AND, OR) for bit operations, and an OUT instruction that writes the operation results of the basic operation instructions to the memory device.
There are instructions required for different types of procedures, but in such conventional examples, the processing time differs between basic operation instructions and OUT instructions.
There is a problem in that even if the program size is the same, the scan time varies depending on the number of OUT instructions.

[Object of the Invention] The present invention has been made in view of the above-mentioned problems, and its purpose is to improve the speed of a sequencer that speeds up arithmetic processing by processing all arithmetic processing in the same amount of time. This relates to arithmetic processing methods.

[Disclosure 1 of the Invention] The present invention includes a first memory device that stores a program, a second memory device that stores data, an address generation circuit that provides an address to the first memory device, and a program that stores a program from the first memory device. Bit selection that selects the bit specified by the program or puts the operation result into the bit position specified by the program according to the program instruction for the data whose instruction and data address are read. and a bit operation circuit that operates to execute a logical operation instructed by a program instruction on a selected bit or to provide an operation result to a previous original bit selection, A feature of the present invention is that the operation of reading out a program instruction, executing a bit operation in a bit operation circuit according to the program instruction, and the operation of writing the operation result to a memory device are executed within the same time.

The present invention will be explained below with reference to Examples.

FIG. 1 shows a circuit configuration adopting the high-speed arithmetic processing method of the present invention, in which a basic clock CLK is generated from a clock generator 7, and the bit arithmetic control circuit 1 uses this basic clock CLK as a reference. creates various timing signals necessary for arithmetic processing.

The memory device (i!2) stores the user program and outputs program data from the address specified by the address data from the address generation circuit 6. The 7 addresses of the address data to be output are increased by +1 in response to the signal CK2.

The latch circuits 8 at 8 b, 8 d, and 8 c are controlled by a timing signal from the bit operation control circuit 1, and temporarily store data of paths B1 and C. The memory device 3 stores the data necessary for sequence calculations and the calculation results, and takes in the latch output of the latch circuit 8d, and also transfers the stored data to the path C.
and is output to the bit selection circuit 4 through the latch circuit 8C.

The bit selection circuit 4 receives data from the memory device e3, takes in the operation result from the bit operation circuit 5 to the bit position specified by the user program input through the latch circuit 8b, and outputs it to the bus D. It is something.

The bit arithmetic circuit 5 calculates the bit selected by the bit selection circuit 4, 4, taste Q7 color: mountain (-Il71
1-4. It performs arithmetic processing as instructed by Ilogerum, and stores the results of the calculation.

Here, the user program includes a 5TRT instruction that instructs bit calculation circuit 5 to set a bit, an AND instruction that instructs an AND operation of the previous operation result and the current bit,
O commands the OR operation of the previous operation result and the current bit
There is an R instruction and an OUT instruction that instructs output of the pre-operation result to the bit selection circuit 4.

The bit configuration of these instructions is as shown in FIG. In other words, an instruction consists of 2 bytes of 16 bits, bus-ba is the first byte of the instruction, bit b is
~b0 is the second byte of the instruction, which is stored in the user program as the first and second bytes, and is read from the first byte.

b) b, 5 to b12 indicate operation codes indicating the type of arithmetic instruction. Also, p) b++~b indicates the bit selection that indicates the position of the specific bit on the data to perform the operation.Since the data is handled as 8 bits, the bit selection that indicates the position from 23=8 is 3 bits. I can express it. bit b
s-50 indicates the data address of memory device 3.

Next, a block diagram showing the movement of instructions is shown in Figure 1, and! #3 This will be explained using the time chart shown in Figure 3.

First, as shown in FIG. 3(a), the calculation is performed by the clock generator 7.
This process is completed with 5 blocks of the basic clock CLK generated by .

First, the data flow is such that when the address of the first byte of the command generated by the address generation circuit 6 is given to the memory device 2 through the bus A as shown in FIG. The byte-th instruction is read. When this first byte instruction is read out, the operation code (bl, to b12) of the first byte instruction is passed through bus B, latched by latch circuit 8a, and given to bit operation circuit 5. The bit selection (b, 1 to b,) is latched by the latch circuit 8b through the bus B, and is applied to the bit selection circuit 4.

Also, a part of the data address of γ)bs is latched by the latch circuit 8d through the bus B, and becomes the address of the memory device ra3. The latch circuits 8 at Bb, 8d are latched at the falling edge of the clock T, and updated at the clock T of the next cycle.

Bit arithmetic circuit 5, which has received the opcode, outputs a control signal to bus E in accordance with the opcode.

The address generation circuit 6 is supplied with the clock CK2, sets the output address to the previous 7 addresses +1, and supplies the address to the memory device 2.

From the memory device 2, the address given is shown in Figure 3 (
As shown in e), the second byte instruction is read. This second byte instruction is latched by the latch circuit 8d through the bus B at the falling edge of the clock T2, and is latched into the latch circuit 8d by the memory device 3.
The address will be Memory device fi3 with fixed address
Computed data is read from. This calculation data is transmitted through bus C at the falling edge of clock T, as shown in #S3 (d
) is latched by the latch circuit 8c. The bit selection circuit 4 selects one bit in response to instructions from the bit operation circuit 5 in the case of a basic operation instruction, inserts a bit in the case of an OUT instruction, and outputs the bus DI as shown in FIG. 3(e).

If it is a basic operation instruction, the bit operation circuit 5 is connected to the bus D.
If it is an OUT command, a write signal is issued to the memory device 3, and data including the operation result is written to the memory device 3.

As described above, the process until the arithmetic data is latched by the latch circuit 8C is the same for both the basic arithmetic instruction and the OUT instruction. Then, the bit operation circuit 5 and the bit selection surface v
By providing I4, basic operation instructions and OUT instructions can be processed in the same amount of time.

[Effect of the Invention 1] The present invention provides a memory device #S1 for storing a program, a second memory lf for storing data, an address generation circuit that provides an address to the first memory device, and a A bit selection circuit that operates to select the bit specified by the program or to put the operation result into the position of the bit to be programmed, depending on the program instruction and the data read from the data address. and a bit operation circuit that operates to execute a logical operation instructed by a program instruction on a selected bit or to provide an operation result to the bit selection, The operation of reading an instruction and executing a bit operation in the bit operation circuit according to the program instruction, and the operation of writing the operation result to the memory device are executed within the same interval -vf, which is different from conventional high-speed arithmetic processing. It is possible to eliminate the processing time difference between basic operation instructions and OUT instructions.
There is no need for separate circuits to perform sequential operations of the PU and bit operations by hardware in parallel processing, resulting in an effect that speeding up can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the bit structure of the same instruction, and FIG. 3 is a time chart for explaining the operation of the same. 2... First memory device, 3... Second memory device, 4... Bit selection circuit, 5... Bit operation circuit,
6...Address generation circuit.

Claims (1)

[Claims] (1) A first memory device that stores a program, a second memory device that stores data, an address generation circuit that provides an address to the first memory device, and a program instruction and data address that are output from the first memory device. a bit selection circuit that selects a bit specified by the program or inputs an operation result into a bit position specified by the program according to a program instruction from the read data; a bit operation circuit that operates to execute a logical operation instructed by a program instruction on the selected bit or to provide an operation result to the bit selection, reads the program instruction from the first memory device, A high-speed arithmetic processing method for a sequencer that is characterized by executing bit operations in a bit arithmetic circuit in accordance with program instructions and writing operation results to a memory device within the same amount of time.