JPS5916007A - Sequence controller - Google Patents

Abstract

PURPOSE:To speed up processing by allowing a bit and a word arithmetic means to read and write data in and out of a storage on time-division basis. CONSTITUTION:A program counter 25 is driven by the output of an oscillator 24. The program counter 25 indicates addresses of a memory 29. Sequence control instructions are supplied to the bit arithmetic means 28 consisting of microprocessor. A gate unit 27 is controlled by the output of the oscillator 24 and the bit arithmetic means 28 and a bit data memory 26 are connected to perform the arithmetic of both. The word arithmetic means 10 operates independently according to a system program memory 22. The word arithmetic means 10 is operated during the period when the sequence instructions are read and written. Therefore, there is no influence upon the speed of the bit arithmetic means 28.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control device that facilitates relay concave path calculation processing, counter timer processing, data calculation processing, and data transfer.

One conventional device of this type is the one shown in Figure 1.

In the figure, (1/4 oscillator, (2j is this oscillator a&(1
) is a spherical counter that increments every oscillation period of (3
1 is a sequence control block memory whose address is given by the output of each stage of the program counter.

(4) is a hit calculation unit, and (5) is a temporary storage memory for hit calculations. (6) is an input section, and (7a) to
(7f is the input terminal. (8) is the output part and (9)
a) to (9f) are output terminals.

Next, the operation will be explained. The oscillator (υ) outputs a constant local number signal f which increments the program counter (2). The program is increased one by one in accordance with the step, and the stored contents of the sequence 7 control program memory (3) are sequentially read out to the data line of the sequence control program memory (3). The contents of the sequence control program memory (3) are a series of logical operation instruction codes.

The sequence control program memory (30 pieces) is stored in advance to satisfy the operations of controlled objects such as machine tools and automatic assembly machines.The human computing unit (4) sequentially reads out the logic Interpret the operation instruction code.

Performs hidden logical operations between the input signals led to the bit arithmetic unit (4) via the external input terminals (7a) to (7f) and the input section (6), and with the logical value output to the output section +8). do.

The logical operation result is finally output to the output section (8).

The controlled object is driven from the output terminals (9a) to (9f).

Hit operator +41 is an arithmetic unit that executes logic operations in 1-bit units at high speed. And from the external output, it seems like logic circuits are working in parallel like a conventional relay control panel.

Conventional sequence equipment as shown in Fig. 1 is built around a human computing unit, so when data processing is required, the only option is to repeat bit operations.
It was practically impossible.

Another conventional device of this type is the one shown in Figure 2.
j) One. In the figure, (10 is a microprocessor, Oυ is an input section, (12a) to (12f) are input terminals, α is an output section, and (14a) to (12f) are input terminals.
(14f) is an output terminal. 0c11.0c11.0c11.0c11.0c11. j) with t sequence control program memory.

Next, the operation will be explained. micro'rosetsusa00
reads a part of the sequence 7 control program memory OQ by the system program stored in the system program memory QFj, determines the code of the word, and executes the logical operation ii+?+i according to the code.

When executing this logical operation, determine the address of the input part that is part of the above code.

From external input terminals (12a) to (12f), input section αb
Select the required input by microprocessor O[)
Read into the calculation section of. After processing a part of the sequence control 1 μgram, read the next part of the system fluorogram C′i to the sequence control program memory Gf9, determine its code, and input the code to perform the logical operation T. Execute. When a code corresponding to an output instruction in a series of sequence control blocks is read from the sequence control program memory Qf9, the system program outputs the previous bit operation result to the corresponding address of the output section (to). .

To complete the processing of part of the sequence 7 control program, follow steps 10 to 207 of the system control program Z. Requires step processing. On the other hand, the data processing command has the characteristic that it can be operated at high speed because the data word length of the microprocessor is 8 bits or 16 bits.

Since the conventional sequence control device shown in the second factor is configured as shown in D, it has drawbacks such as high speed data processing and slow bit operation processing.

Another conventional method is a device as shown in FIG. 8, which combines a micro 10 setter oQ and a bit arithmetic unit (4). In the figure, (e) is a pit data memory for temporary storage during bit operations and for turning on inputs and outputs.

OFF hit information is stored. ■ is a two-way gate and J
), (101) is a control line that controls the bidirectional connection and selects the path connected to the human data memory. (102) is a bit operation address/data correction. The control line/line (101) ζ connects the data of sequence control 1 program memory (3) to the microprocessor. (100) i-flag line, It is possible to exchange start/stop requests between the microprocessor αQ and the hit calculator (4). Figure 4) is an example of a tourogram, which shows the contents of the sequence control program memory.

FIG. 5 is an operation timing diagram of this example (L4 1.
G11e indicates the operating status of the microprocessor. (48a) to (48e)
, (δOa) to (50e) indicate the progress of the operation and move from a to e.

Next, the operation will be explained.

The flocram counter (2) is & the first 0, and the sequence control flocram memory (3) takes the bit instruction of step 0 to the hit operator (April). This is an instruction or a bit operation by hook line (1
00) to the microprocessor o(J).

Therefore, microprocessor OQ does not operate.

The control line (101) also connects the bit operation address/data path to the human data memory (e) through the bidirectional gate (2). MJ, 1m (48a)
During the interval, the hit operation is executed, and then the oscillator (by the signal from υ)' program counter (21) approaches, and the hit command of step l is passed to the hit operator (4th C). (48b) is executed, the program counter (2) increments the first step, and when the word instruction in step 2 is passed to the human operator, the bit operation!?4 (4)
It performance rest l: Period (48c) $2: Enter, through the hook line (100), inform the microprocessor (10 that it is a word operation. At the same time, to the two-way gate ■ and one-sided gate) the control line (1
01) Connect the output data of the sequence control 1 program memory (3) and the address and data lines of the bit data memory (e) to the address/data path Q1 of the microprocessor. Through the line (101), the oscillation of the device (1) is stopped.The microprocessor detects the word operation instruction (J) through the flag line (100) and sends it to the one-way gate.
The program counter (2) is first read out through , the program counter (2) is advanced, the variable address of the word operation is read, and the word operation is executed during the period (50b).

After the execution is completed, the word operation completion is transmitted to the bit operation unit (4) fζ through the flag line (100). Bitwise operation unit (
In April, the two-way gate ■ and the one-way gate a are controlled by the human operator 1, and at the same time, the oscillator (1) is restarted.
Step (Continuously executes the instruction in step 8. - The microprocessor enters the sleep period or interrupts by the timer are accepted, and the contents of the timer tape in the word data memory are updated. -The above operation is sequence 7
It is repeated according to the control program. After lFj, when the end command is sent to the hit calculator (4), the microprocessor OF1 learns this jl through the let flux line (100), enters the period (50e), and reads the contents of the hit data memory (e). At the same time as outputting to the output section -, the external signal is read from the input section 0υ and written to the bit data memory (E). after that.

Flow counter (21 is set seven times and steps are taken.

Execute the sequence control Grodarum from O.

Since the conventional Sequence 7 controller is configured as described above, it takes time to execute the entire program because the bit operation and word operation are in operation while the other is at rest. In order to monitor the activation of word operations from the sequence control program, changes to the sequence control program, such as monitors, must be performed during hit operation pauses.

The drawbacks are that bit operations are masters and word operations are fixed due to the Nurep relationship, which is inconvenient for data processing-based applications.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it eliminates the need to share the middle stage of human operations and word operation means or data memory in a time-sharing manner, and enables high-speed bit operations and high-speed data operations. The purpose of this project is to provide a sequence 7 control device that smooths the surface of the river.

Another purpose of this town is to use cjl and other calculation means.

RT to share the sending/receiving means or data mesori in a time-sharing manner.
The object of the present invention is to provide a sequence control device having seven input/output functions with good responsiveness.

Another object of the present invention is to provide a program counter.

The word operation means and the sequence 7 control program memory are shared in a time-division manner, and the sequence control program σ)i is also used for execution of a series of operations. The purpose is to

An embodiment of the present invention will be described below with reference to drawing numbers.

In FIG. 6, the ring is composed of a microprocessor, a word calculation means, a system program memory of the microprocessor, a data calculation processing timer, and a program for executing counter processing.

(1) l-
1 This program [inputs m, t controlled by ζ
soa) to (80f)i are input terminals. G is an output section that is controlled by the above input/output control flocram.

(81a) to (81f) are output terminals. CA is a word data memory that stores data during word data processing.

(Incorporated) is an oscillator, (C) is a blockram counter for performance driven by this oscillator, and (2) is a sequence 7 control program memory read out by this blockram counter. (c) is a bit operation means.

(E) is a human data memory. @ is a gate unit that uses one oscillator (c) to periodically connect the word operation means to the hit data memory (e) or the bit operation means (c) to the hit data memory (e).

Further, the gate unit 10 connects the program counter (2) and the word arithmetic unit, or connects the sequence 7 control programm memory (2) and the word arithmetic unit, according to instructions from the word arithmetic means. The lead transmits an interrupt request from the hit calculation means (c) to the word calculation means through an interrupt request line. (Incorporated) is an address/data banu word operation means iζ
More controlled. FIG. 7 shows the timing of connections between the bit data memory (E), the word operation means and the bit operation means (C). Sasai: 1 hour,
91j This is the first period in which the data memory and the word calculation means (g) are continuously operated.

Next, the program counter (C) is driven by the output signal of the oscillator (2).

The output of each stage of the program counter (c) drives the address line of the sequence control programm memory via the gate unit (c), and the sequence control command is transferred from the sequence control programm memory to the bit operation means ( On the other hand, in synchronization with the input, the output of the oscillator (A gate unit) is controlled, and the bit calculation means (C) and the hit data memory (E) are connected. The receiver executes a hit operation between the bits of the hit data memory (e) according to the control command it takes, and holds the operation result in the bit operation result register in the hit operation means (c). fl writes the contents of the operation result register to the human data memory (E) (... Word operation means Q (J is the system program memory (2)).
Accordingly, it operates independently of the bit operation means □□□ and performs various data processing. The word operation means outputs the operation result of the bit operation means @, if necessary, allocates it to the data memory (c) and outputs one nail from the address/data path (41-), and enters the standby state.

The oscillator @ controls the gate unit at high speed.

Since the connections between the human data memory (E), the word calculation means (2), and the human performance means (C) are switched as described above, the above standby state is released within one time (t).
During the period Ov in the figure, the word operation means (7) can read the contents of the human data memory (E). 1 required for sequence control (external input information is input from input terminals (80a) to (8
0f) and input section 4 into the word calculation means (1), and can be written into the human data memory (a) fL. Similarly, the sequence control information calculated by the human calculation means (c) is written to the human data memory (c), read out to the word calculation means (c), and then output to the output section. , output terminals (81a) to (81f)
is output as a control output.

If there is a word data processing instruction in the sequence control program, it detects 14.bit operation means (4) or 7'l and sends an interrupt request to the word operation means clause to the 1 interrupt request line -. When the word operation means receives an interrupt request, it takes priority over the currently executing program.
J rank is determined, and if the priority level of the interrupt request from the hit calculation means (c) is high, it controls the gate unit ■ and reads the contents of the sequence control program memory (4).
Know the interrupt cause and perform the necessary processing. Once word data processing is complete.

The result is written to the bit memory, and then the bit operation means ← or the operation is continued using it.

Figure 8 shows a specific example of this generator. 14 is applied to the pulse input of C104).
address lIMiζ) is added to the program memory. (105) is the srtmm output line of the program counter ■.

It is connected to the switching control terminal of the atres puff switching gate and the data path switching bidirectional gate ([i3).

(106) is 8 bits in the data line fi++ of the control block memory. button) is an 8-bit latch.

(107) is the output of the latch. C109) The address line of the liHIF tool means, (108) is the data line.

<111) i, t ward)' Address path of Si1 means, (110) is a data line. (112) is the address line of the bit data memory (a), (11
8) is a data line.

FIG. 9 shows the structure of the command words of the sequence control program. - indicates memory with a word length of 8 bits, (5
4a) to (54d) are addresses of this memory.

(55a) and (55b) are the steps of the sequence control program. 1 step' is 5 bits + 5 bits.
O) The naming word length is 16 bits, with the upper 8 bits at even addresses.

The lower 8 bits are stored at odd addresses.

FIG. 10 is a timing diagram illustrating the operation of the embodiment of FIG. 8. (59a) is the signal waveform of the lowest output line (105) of the blockrum counter, state is the number Jo1 of the instruction code output on the data M (106) of the sequence control block memory wire, and (59a) (
59b) is output as the upper rank, T- rank, at number /1114.

- is a latch command pulse for an 8-bit latch lock, and symbol - is a write pulse for the human operation result. The haze indicates the switching status of the address bus and data bus of the human data memory, C68a) indicates the period during which it is connected to the word operation means, and (68b) indicates the period during which it is connected to the bit operation means.

Next, the operation Eζ will be explained. When the content of the program counter is II OII, the content of address 0000 of the sequence control program memory is outputted to the data line (106) and latched with an 8-bit lunch.

This is the upper 8 bits of the instruction code of step R1 of the sequence control program.Next, the oscillator (c) advances the program counter () to address 00.
The content of 01 is output as 1 on the data line (106).

The key is the lower 8 bits of the instruction code of the first step. From this point on, the upper 8 bits and lower 8 bits that are the output of the latch value υ are added to the example of the hit calculation means tL, and the hit calculation is executed f(.This execution period is (6) in FIG.
8b), and in this period, the address and data bus of the lowest output l1lj1 (105) of the program counter (from Iζ to the bit operation means) are transferred to the data memory (105) by controlling the switching gate Ii+5.
e) because it is connected to the address and data lines.

Bit operations can be performed using the contents of the human data memory (e) as data. - When reading and writing information from the 10,000 word calculation means or the human data memory (e).

This is carried out during the period (68a), that is, while the upper 8 bits of the sequence control program are being read.

During the period (68a), since the switching gate control is controlled by the lowest output of the program counter as described above, the bus of the word processing means and the human data memory (e) are connected.

As described above, in the example A of this invention, the word operation means accesses the bit data memory during the reading period of the upper S bits of the sequence-based h program, so the operation speed of the hit operation means (c) is not reduced. , word operations can also be performed.

FIG. 11 shows another embodiment of the present invention. In the figure, the target is the transmitting/receiving means, and the symbol is the signal transmission line. The other components are the same as those in FIG.

FIG. 12 is a timing diagram for explaining the embodiment of FIG. 11, and shows the operation of the gate unit.

Oscillator Hj drives one gate unit. The gate unit also has a bit data memory (as shown in Figure 6).
(e) and bit operation means (c) are connected for period (1), and bit data memory (2) and word operation means - are connected to Ij
The bit data memory (e) and the transmitting/receiving means (6) are connected for a period of 50 seconds. In this way, the results of the hit operation and word operation are read out to the transmitting/receiving means via the hit data memory (e).

It can be transmitted to a long distance via a signal transmission line. Information from a distant place can be received via a signal transmission line, written into a bit data memory, and can be used as input information for hit operations and word operations. First, in the present invention, there is no need to suspend transmission and reception until a series of calculations are completed, and a remote input/output function with good responsiveness can be achieved.

In addition, in the above embodiment, only the time-sharing connection between the bit data memory (e) and other means in the gate unit was explained. Chest, Sequence: AI! Add a function to time-share the connection between the control block memory and the word calculation means.

It is possible to read and write the sequence control program during bit operation IK operation.

As described above, according to the present invention, it is possible to control the timing between the bit data memory and the word calculation means, the hit calculation means, and the transmission/reception means, and between the sequence control program memory and the program counter and the word calculation means. Try to connect it by dividing it into 1.

Human operations and word operations that are related to each other can be executed at high speed, programs can be easily created independently of each other, and the sequence program monitor link 5 and It is easy to change, and has the effect of providing a remote input/output function with good responsiveness.Also, by using the word calculation means to count the internal interrupts of the timer at a constant period based on the human calculation results, it is easy to use. You can get a timer function,
By counting the bit rji calculation results using the word calculation means, there is also an effect that an Eζ counter function can be easily obtained.

[Brief explanation of the drawings] Figure 1 is a block diagram of a conventional sequence control system.
FIG. 2 is a block diagram showing another conventional sequence control device, FIG. 8 is a block diagram showing still another conventional sequence control device, and FIG. 4 is an example of a program for explaining FIG. 8. An explanatory diagram showing. 5 is a timing diagram of FIG. 8, 6C is a block diagram showing a sequence control device according to an embodiment of the present invention, FIG. 7 is a timing diagram explaining an embodiment of this invention, and FIG. A block diagram showing a specific example of an embodiment of the present invention,
FIG. 9 is an explanatory diagram showing the structure of the command word of the program of the embodiment of FIG. 8, FIG. 10 is a timing diagram of the example of FIG. 8, and FIG. 11 is a block diagram showing another embodiment of the present invention. , 1st
FIG. 2 is a timing diagram illustrating another embodiment of this invention. In the figure, (c) is a bit operation means, (e) is a bit data memory (storage means or first storage means), one phrase is a word operation means, the function is a transmitting/receiving means, and (2) is a sequence control program memory (the first storage means). (2) storage means). Note that the same line numbers in Figure 1 indicate the same or equivalent parts. Agent Makoto Shimano - 11th Figure 2 Figure 3 ttti Figure 4 Figure 5 Figure 7 Fukuso "Rikomi Nuku, 1 Ri Figure 6 Figure 71-1 Figure 8 Figure 9 Figure 10 Figure 0 Continuation Amendment (spontaneous) 1978 I1 Kotai Date: 3 Person making the amendment 0, fm it: LIJ J! M Column 6 of the detailed explanation of the invention in the specification, Contents of the amendment (1) Clear A (Correct the following in the IT document.

Claims (1)

[Claims] (Comprising four means for one-hit performance, a storage means for storing input information, output information, and internal temporary record information, and a word calculation means, the storage means 0) Memory writing, reading A sequence control device characterized in that the bit operation means and the word operation means perform the operation in a time-sharing manner. (2) The bit operation means, input information, output information, and internal temporary storage. It has a memory means for storing information, a word operation means, and a transmitting/receiving means, and the memory writing and reading of the memory means are carried out in a time-sharing manner by the bit operation means, the word operation means, and the transmitting/receiving means 1. A sequence control device characterized in that: (3) a hit calculation means, a first storage means for storing input information, output information, and internal temporary storage information; and a first storage means for storing a sequence control program. 2 storage means and a word operation means, the memory writing of the first storage means;
The reading is carried out in a time-sharing manner by the bit operation means and the upper t-word operation Teshima, and
A sequence control device characterized in that the memory readout of the second storage means is carried out in one time division by the word calculation means and the hit calculation means. (4-no-hit calculation means; a first storage means for storing input information, output information, and temporary storage information;
It has a second storage means for storing a sequence control program, a word operation means, and a transmitting/receiving means, and the writing and reading of the memory in the first storage means is performed by the bit operation means, the word @ calculation means, and the transmitting/receiving means. 1. A sequence control device characterized in that the storage and readout of the second storage means are performed in a time-division manner by the word operation means and the bit operation means.