JPS61175834A - Data processor provided with microprogram debug function - Google Patents

Abstract

PURPOSE:To improve the efficiency of a microprogram debug by constituting a titled device so that a stop of a microprogram operation of a CPU, and readout/write of a designated address of a control storage can be executed in accordance with a request of a support processor. CONSTITUTION:In case when it is desired to execute a debug of a microprogram of a CPU10, a support processor 20 sends an operation stop request to a CPU control part 12 through a serial bus 60, and sets a program debugging mode. In case when the CPU10 has executed readout/write of a designated address of a control storage 11 by stopping a microprogram operation, the support processor 20 or a microsequencer 19 holds an execution address of its stop time in the course of a series of operations. Accordingly, by resetting this address through the CPU control part 12, and restarting a clock generator CG17, the processing of the microprogram can be continued without deteriorating the continuity before and after the stop.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing device with a microprogram debug function capable of debugging a microprogram of a CPU.

[Technical background of the invention and its problems] In the conventional micro-70gram control type data processing device, debugging of the CPIJ microprogram is carried out by a device having unique and limited functions. Its operation was also complicated. For this reason, it has conventionally been difficult to efficiently debug microprograms.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to provide a data processing device with a microprogram debugging function that can realize a microprogram debugging tool that is highly capable and easy to operate. .

[Summary of the Invention] According to the present invention, there is provided a support processor that performs execution control of microprogram debugging, a rewritable control memory that stores a microprogram, and a stop of microprogram operation in response to a request from the support processor. Also provided is a data processing device with a microprogram debugging function, which includes a CPU having a CPU control unit that reads/writes microinstructions. The CPU control unit in the CPU includes a stop means for stopping the microprogram operation of the CPU (J) when the request from the support processor is a request to stop operation, and a stop means for stopping the microprogram operation of the CPU (J) when the request from the support processor is a read request. means for causing a specific device inside the CP port stopped by the stopping means to perform one clock operation and reading data from an address in the control memory specified by the support processor; In this case, the specific device inside the CP port that has been stopped by the stopping means is caused to perform one clock operation, and the write data from the support processor is written to the address of the control memory specified by the support processor. The microcontroller is equipped with means for successively issuing/writing microinstructions for each step necessary for microprogram debugging in response to a request from a supporting processor.

[Embodiment of the Invention] FIG. 1 shows the configuration of a data processing device with a microprogram debug function according to an embodiment of the invention. In the figure, 10 is a CPU, and 20 is a support processor that controls the execution of debugging of the microprogram of the CPU 10. In CP tJ 10, 11 is a rewritable control memory that stores various microprograms;
12 is a CP in response to a request from the support processor 20.
This is a CPU control unit that stops the microprogram operation of U10 and reads/writes microinstructions.

The control memory 11 includes a microinstruction register (hereinafter referred to as MAR) that holds microinstructions read from the control memory 11.
13 and the output of a write register 14W that holds write data for the control memory 11, respectively, by signal lines 31. MIR1
The output of 3 is sent to the read register 14R by the signal line 32.
and each input of the register 15 for microinstruction execution. The output of the read register 14R is on the signal line 3.
3, the inputs of the write register 14W are all connected to the CPU control unit 12 via the signal line 34.

The clock input of the MIR 13 is connected to the output of an OR gate (hereinafter referred to as 'OR') 16 via a signal line 35. One input of 0R16 is clock generator 1, which will be described later.
The other input of 0R1B is connected to the signal line 36 that transmits the clock signal CLK synchronized with the clock signal generated from 7, and the other input of 0R1B is connected to the signal line 37 that transmits the clock signal CLK1.
is connected to the CP (J control unit 12).

The clock signal CLK is also supplied to the clock input of the R register 15. The clock input of the read register 14R is connected to the CPIJ control unit 12 by a signal line 38 that transmits a clock signal CLK2, and the clock input of the write register 14W is connected to a signal line 39 that transmits a clock signal CLK3.

A clock generator 17 (hereinafter referred to as CG) is necessary for the operation of the CPU 10 and generates a lock signal.

The CG 17 is connected to the CPU control unit 12 by a signal line 41 that specifies to stop the clock generation operation of the CG 17. 18 has inputs A, B, and S, and a selector (
(hereinafter referred to as SEL).

Input A of the 5EL18 is connected to the CPU control unit 12 by a signal line 42, and input B is connected to the MI control unit 12 by a signal line 43.
Connected to R13. The signal line 43 is used to transmit the contents of the address part (branch address part) of the microinstruction held in the MIR 13. Further, the input S of the 5EL 18 is connected to the CPU control section 1 of the MIR 13 by a signal line 44.

The output of 5EL113 is control record I! It is connected by a signal line 45 to a microsequencer 19 that generates 11 addresses. The microsequencer 19 is connected to the CPtJPt upper control via a signal line 44 and to the MIR 13 via a signal line 46, respectively. The signal line 46 is used to transmit the contents of the branch specification section of the microinstruction held in the MIR 13. Micro sequencer 1
The address generated in step 9 is supplied to the address input of control memory 11 via signal line 47.

CP LJ 10 and support processor 2o are interconnected by system bus 50. Also cPU(
The CPU control section 1 and support processor 20 within the CPU control section 1 and the support processor 20 are interconnected by a serial bus 6o. Note that in FIG. 1, the main storage device and the like are omitted.

Next, the operation of one embodiment of the present invention will be explained.

In the CPU 10, the microsequencer 19 generates an address to be executed next. The address generated by the microsequencer 19 is supplied to the control memory 11 via the signal line 47, whereby the microinstruction is retrieved from the corresponding address in the control memory 11. The microinstruction taken out from the control memory 11 is supplied to the MIR 13 via the signal line 31, and is held in the MIR 13 by supplying the clock signal CLK synchronized with the glue lock signal from the CG 17 to its clock input. The clock signal CLK is also supplied to the clock input of the R register 15. As a result, the microinstructions held in the MIR 13 are held in the register 15 via the signal line 32.

Each bit of the predetermined field of the microinstruction held in the register 15 (or the decode signal of the predetermined field)
is led to each part within the CPU 10, and each part is controlled thereby. The contents of the address part of the microinstruction held in the MIR 13 are sent to the SEL 18 via the signal line 43.
The content of the branch specification section is supplied to the input B of the signal line 46.
The signal is supplied to the microsequencer 19 via the microsequencer 19. 5E1
18 is the content of input B in the normal state (0 in microprogram debugging mode to be described later);
That is, the contents of the address field are selected. The contents of this address field are transmitted to the microsequencer 19 via the signal [145].
supplied to The micro sequencer 19 has a built-in +1 circuit that increments the previously generated address by 1. In the normal state, the output of this +1 circuit or the content of the address field (branch address) selected by 5E118 is sent to the branch specification field of the microinstruction. Select according to the content and output the next execution address. In addition to the above-mentioned addresses, the microsequencer 19 also has the function of selecting the start address of a series of microinstruction processing specified by a macroinstruction, an address specified when an interrupt occurs, etc. A detailed explanation regarding this point will be omitted since it is not directly related to this invention.

Now, when the support processor 20 wants to debug the microprogram of the CPU 10, the support processor 20 (CP
Generates an operation stop request (requesting to stop the operation of the microprogram of IJ 10) and sends the same request to the serial bus 60.
The data is sent to the CPU control section 1 in the CPU 10 via the CPU 10. The signal line 41 is set to 0 in response to an operation stop request from the CPU control unit 1 upper 2 support processor 20.
Stop the operation of FFL and CG17. This allows C.P.
The generation of the lock signal is stopped as necessary for the operation of U10. As a result, the microprogram operation of the CPU 10 is stopped. This stopped state is called microprogram debugging mode. When the execution of the operation stop request from the CPU control unit 1 upper 2 support processor 20 is completed, that is, when the CPU IJ 10 is set to the microprogram debugging mode (hereinafter referred to as MPD mode), the interrupts the support processor 20, and notifies the support processor 20 of this fact. Thereby, the support processor 20 recognizes that the microprogram operation of the CPU 10 has been stopped, that is, that the MPD mode has been set.

When supporting processor 20 wants to read the contents (microinstructions) of control memory 11 in MPD mode, it transfers a desired address and a read request to CPU control unit 12 . In response to the read request from the support processor 20, the CPU control unit 12 reads the address specified by the support processor 20 via the signal line 42 to 5EL.
18 and turns on the signal line 44. 5EL18, when the signal line 44 is in the ON state, the input A
, B, the content of input A, i.e., the support processor 20
The address specified by is selected and supplied to the microsequencer 19 via the signal line 45. Micro sequencer 1
When the signal line 44 is in the ON state, 9 selects the address from the 5EL 18 regardless of the state of the signal line 46, and supplies it to the control memory 11 through the signal line 47. As a result, the corresponding microinstruction is read onto the signal line 31 from the address in the control memory 11 specified by the support processor 20. In response to a read request from the support processor 20, the CPU control section 12 outputs the clock signal CLK1 for one clock onto the signal line 37. This clock signal CLK1 is applied to M via 0R16 and signal line 35.
It is fed to the clock input of IR 13, which causes the microinstructions on signal line 31 to be held in MIR 13. Further, the CPU control section 12 outputs the clock signal CLK2 for one clock onto the signal line 38 when a certain period of time has elapsed after outputting the clock signal CLKI. This clock signal CLK2 is supplied to the clock input of the read register 14R, so that the microinstruction held in the MIR 13 is taken into the read register 14R via the signal line 32. When the CPU control unit 12 completes the above operations, it issues an interrupt to the support processor 20. The support processor 20 reads the contents of the read register 14R via the serial bus 60, the CPU control unit 12, and the signal line 33 in response to an interrupt from the CPU control unit 12 in response to a read request, and performs processing necessary for debugging. .

Next, a write operation to the control memory 11 in the MPD mode will be explained. The support processor 20 is an MPD
When it is desired to write a desired microinstruction to a desired address in the control memory 11 in this mode, the address and write request are transferred to the CPU control unit 12 via the serial bus 60. The support processor 20 also transfers desired write data (microinstructions) to the CPU control unit 12. In response to a write request from the support processor 20, the CPU control unit 12 outputs the write data from the support processor 20 onto the signal line 34, and also outputs the O-clock signal CLK3 onto the signal line 39 for one clock cycle. As a result, the clock signal CLK
3 is supplied to the clock input of write register 14W;
Write data on the signal line 34 is held in the W register 15. Further, in response to a write request from the support processor 20, the CPU control unit 12 performs address control similar to that in the case of a read request. Thus, the address specified by the support processor 20 is selectively outputted from the microsequencer 19 to the control memory 11. As a result, the contents of the write register 14W, that is, the write data (microinstruction) transferred from the support processor 20 are written to the address of the control memory 11 designated by the support processor 20. At this time, it is also possible to output one clock signal CLK1 from the CPU control section 12 onto the signal line 31 and load the write data into the MIR 13.

As described above, according to this embodiment, the microprogram operation of the CPU 10 can be stopped and the specified address of the control memory 11 can be read/written in response to a request from the support processor 20, so that microprogram debugging can be performed. Efficiency can be improved.

・By the way, the microprogram operation of the CPU 10 is stopped and the designated address of the control memory 11 is read/
When writing is performed, if the support processor 20 or microsequencer 19 retains the execution address at the time of the stop during the series of operations described above, the same address is reset through the CPU control unit 12 and the CG
By restarting the microprogram 17, it becomes possible to continue processing the microprogram without losing continuity before and after the stop.

In addition, in the configuration shown in FIG. 1, in the MPD mode, the support processor 20 performs address adjustment for the control memory 11 as described above, and operates the CG 17 for one clock through the CPU control section 12, thereby controlling one part of the microprogram. It is also possible to execute each step.

Note that microprogram debugging can be made more efficient by connecting a CRT display terminal or the like to the support processor 20 and operating the terminal to issue the above-mentioned operation requests and display the necessary information on the screen. I can do it. In addition, by adding the debug function described above to the support processor for maintenance diagnosis, CP
Centralized management of U becomes possible.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to realize a microprogram debugging tool that is highly functional and easy to operate.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing device with a microprogram debugging function according to an embodiment of the present invention. 10...CPU, 11...Control memory, 12...C
PU control unit, 13... Micro instruction register (MIR), 14R... Read register, ? 4W...
・Write register, 17...Clock generator (CG)
, 18... Selector (SEL), 20... Support processor, 50... System path, 60... Serial bus.

Claims (1)

[Claims] A support processor that controls the execution of microprogram debugging, a rewritable control memory that stores the microprogram, and a CPU control that stops the microprogram operation and reads/writes microinstructions in response to requests from the support processor. and a CPU having a stop means for stopping the microprogram operation of the CPU when the request from the support processor is an operation stop request, and a stop means for stopping microprogram operation of the CPU when the request from the support processor is a read request. means for causing a specific device inside the CPU stopped by the stopping means to perform one clock operation and reading data from an address in the control memory specified by the support processor, and when the request is a write request; and causing one clock operation to be performed only on a specific device inside the CPU that has been stopped by the above-mentioned stopping means,
A data processing device with a microprogram debugging function, comprising means for writing write data from the support processor to an address in the control memory specified by the support processor.