JPH04309139A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form a non-volatile memory, which can reload a program, and an ICE circuit on a chip and to change the contents of the non-volatile memory by the ICE circuit. CONSTITUTION:A non-volatile memory 1 stores the program so as to reload it, and a central processing unit(CPU) 2 is composed of an address generation circuit 2a equipped with a program counter 2b to perform access to the prescribed address of the memory 1 and a program execution part 2c for the read- out program. A RAM 3 stores data used for executing the program. An ICE circuit 4 controls and supervises the operation of the CPU 2, a first stop control means 5 stops the operation of the program execution part 2c based on a write control signal inputted from an outside ICE device and a write control means 6 inputs address data inputted from the outside ICE device to the address generation circuit 2a and writes program data in the prescribed address of the memory 1 accessed by the address generation circuit 2a.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an ICE (in-circuit emulator) circuit mounted on a chip. In recent years, when debugging a program while actually running a high-speed processor such as a DSP (digital signal processor) or RISC (reduced instruction set computer), the operating frequency at which the program is actually used is Must run on the processor. For this reason, an ICE circuit that can follow higher operating frequencies has become necessary.

0002

[Background Art] Conventionally, high-speed operating RISC chips are equipped with an ICE circuit, and this ICE circuit traces the status of the processor in operation and the execution address of the program, and sets breakpoints to stop the program. etc. Furthermore, the processor does not have an internal program memory, and only accesses external memory through an external bus.

On the other hand, it is also necessary to form an ICE circuit on the chip in a DSP that operates at high speed, but in order to achieve higher speed, this DSP stores the program executed by the CPU in an EPROM formed on the chip. Ori,
Furthermore, data is also processed using a RAM or the like formed on the chip. In particular, one-chip D
In the case of SP, there are problems in that the number of external terminals related to input/output interfaces increases, and the number of external interface terminals that can be assigned to the ICE circuit on the chip is also limited.

Therefore, when an ICE circuit is formed in a semiconductor integrated circuit device in which an EPROM is formed on a chip, it is necessary to be able to rewrite the contents of the EPROM on the chip. Furthermore, an ICE circuit that can trace data on a RAM formed on a chip is required. Furthermore, it is necessary to reduce the number of external interface terminals allocated to the ICE circuit on the chip.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit device in which a programmable non-volatile memory is formed on a chip. The purpose is to be able to change the contents of nonvolatile memory using a circuit.

Another object of the present invention is to be able to trace the execution address of a program and also trace data of a RAM formed on a chip. Another object of the present invention is to be able to reduce the number of external interface terminals allocated to the ICE circuit on the chip. Another object of the present invention is to enable the central processing unit of a semiconductor integrated circuit device to be operated by a monitor program of an external ICE device.

A further object of the present invention is to be able to stop the function of the ICE circuit when the ICE is stopped.

[0008]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. The nonvolatile memory 1 stores programs and is rewritable. The central processing unit 2 includes an address generation circuit 2a including a program counter 2b that accesses a predetermined address of the nonvolatile memory 1, and a program execution unit 2c that executes read program data at high speed.
It is equipped with The RAM 3 stores data used to execute programs.

The ICE circuit 4 controls and monitors the operation of the central processing unit 2 based on instructions from the outside.
The first stop control means 5 provided in the ICE circuit 4 stops the operation of the program execution section 2c based on the write control signal input from the external ICE device, and the write control means 6 stops the operation of the program execution section 2c based on the write control signal input from the external ICE device. address data is input to the address generation circuit 2a, and the address data is input to the address generation circuit 2a.
The program data is written to the predetermined address of the nonvolatile memory 1 accessed by.

The ICE circuit also includes a data format conversion means for inputting parallel signal data in a semiconductor integrated circuit device and converting it into serial signal data, and a central processing unit that converts the serial signal data converted by the data format conversion means. and a plurality of serial interface ports for outputting other status information to an external ICE device. Also, ICE
The circuit includes a synchronization clock generator in the ICE circuit for serial data transfer with the ICE main body of an external ICE device, and encodes serial signal data of any one serial interface port based on the clock signal. The ICE is equipped with a modulation circuit that simultaneously transmits serial signal data and a synchronized clock to the ICE main body.

The ICE circuit also includes a plurality of registers for tracing data stored in the RAM,
An identification code is added to the data in each register and the data is sequentially transferred to the data format conversion means. The ICE circuit also includes a second stop control means for temporarily stopping the operation of the central processing unit according to a program in the nonvolatile memory based on a break control signal from an external ICE device; The contents of the program counter and status register are changed based on the stoppage of the processing unit.
A switching control means is provided for saving the program to a memory within the ICE main body, and thereafter switching access of the program from the nonvolatile memory to the memory of the ICE main body to cause the central processing unit to execute the monitor program of the external ICE device.

Furthermore, the ICE circuit includes a function stop means for stopping the function of the ICE circuit based on a function stop signal from an external ICE device.

[0013]

[Operation] Therefore, according to the first invention, the first stop control means 5 provided in the ICE circuit 4 controls the program execution unit 5 based on the write control signal input from the external ICE device.
Since the operation of c is stopped, even if a predetermined address of the nonvolatile memory 1 is accessed by the address generation circuit 2a and the program is read, it is not executed, and the write control means 6 writes to the predetermined address of the accessed nonvolatile memory 1. The program data is written.

The ICE circuit also includes a data format conversion means for inputting parallel signal data in the semiconductor integrated circuit device and converting it into serial signal data, and a central processing unit and the serial signal data converted by the data format conversion means. By equipping the IC with multiple serial interface ports that output other status information to an external ICE device, the IC
The number of ports allocated to the E circuit is reduced.

[0015] Furthermore, the ICE circuit can be connected to an IC of an external ICE device.
The ICE circuit includes a synchronization clock generator for serial data transfer with the E main body, and a modulation circuit that encodes the serial signal data of any one serial interface port based on the clock signal. Serial signal data and synchronized clock at the same time
By sending the signal to the CE main body, there is no need to provide a port used only for synchronization, and the number of ports allocated to the ICE circuit can be further reduced.

[0016] Furthermore, the ICE circuit is provided with a plurality of registers for tracing data stored in the RAM,
By adding an identification code to the data in each register and sequentially transferring the data to the data format conversion means, it becomes possible to trace a plurality of data almost simultaneously. The ICE circuit also includes a second stop control means for temporarily stopping the operation of the central processing unit according to a program in the nonvolatile memory based on a break control signal from an external ICE device; When the processing unit stops operating, the contents of the program counter and status register are saved to the memory within the ICE main unit, and thereafter, program access is switched from non-volatile memory to the memory within the ICE main unit, and the central processing unit is accessed from the external ICE device. By providing a switching control means for executing a monitor program, it becomes possible to place the central processing unit under the control of an external ICE device at an arbitrary address in the nonvolatile memory.

Furthermore, by providing the ICE circuit with a function stop means for stopping the function of the ICE circuit based on a function stop signal from an external ICE device, the ICE circuit can be stopped.
When the circuit is not in use, no trouble occurs in the operation of the semiconductor integrated circuit device.

[0018]

[Embodiment] An embodiment in which the present invention is embodied in a DSP will be described below with reference to FIGS. 2 to 5. As shown in FIG. 2, a DSP 11 and a peripheral circuit 12 are mounted on the user board 10. The DSP 11 is connected to the ICE main body 13 and the terminal computer 1 via a buffer box (not shown).
4 external ICE devices 15 can be connected.

The DSP 11 includes a central processing unit (CPU) 17 and an E memory section 1 formed on one semiconductor chip 16.
8, an input/output circuit (I/O) group 19 and an ICE circuit 20. As shown in FIG.
8 has an EPROM 21 as a non-volatile memory, the first,
Second RAM 22, 23, each I/O of the I/O group 19
A plurality of registers 24 and 25 (8 in this embodiment) corresponding to
) data trace registers 26a to 26h, IC
A control register 27 for the E circuit 20, a status register 28 for the ICE circuit 20, breakpoint registers 29a, 29b, etc. are provided, and these are connected via a data bus 30 to an arithmetic unit 33 constituting the CPU 17. .

A simple instruction program executed by the CPU 17 is stored in the EPROM 21, and its contents can be rewritten. The first and second RAMs 22 and 23 store data used to execute programs. The data trace registers 26a to 26h contain the EP data.
8 consecutive addresses in RAM 22 or 23 based on the trace program stored in advance in ROM 21
Each data is stored separately. Data for controlling the ICE circuit 20 is sequentially rewritten in the control register 27, and the current state of the ICE circuit 20 is written in the status register 28. Further, a program stop address for stopping the CPU 17 is stored in advance in each of the breakpoint registers 29a and 29b.

As shown in FIG. 3, the CPU 17 includes an instruction decoder 31, a control circuit 32, an arithmetic unit 33, an address arithmetic unit 34 as an address generating circuit, a clock generator 35, and the like. The instruction decoder 31 decodes the program data read from the EPROM 21 based on the count value of a program counter (PC) 36 provided in the address calculation unit 34, outputs the decoding result to the control circuit 32, and also decodes The result is output to the arithmetic unit 33 or address arithmetic unit 34.

The control circuit 32 controls the arithmetic unit 33 and the address arithmetic unit 34 based on the decoding result of the instruction decoder 31, and also outputs the status signal ST consisting of a plurality of bits of the CPU 17 to the interface circuit section 38 of the ICE circuit 20. It is supposed to be done. Further, when the control circuit 32 receives a reset signal from the ICE main body 13 while the ICE main body 13 is connected, all processing is interrupted.

The arithmetic unit 33 stores status registers 3 such as carry, zero, overflow, and not-zero flags.
3a, reads data from each RAM 22, 23 based on a control signal from the instruction decoder 31, and executes a predetermined operation based on the read data. Further, the address calculation unit 34 includes the EPROM 21 and the RAM 22.
, 23, registers 24 and 25, data trace registers 26a to 26h, control register 27, status register 28, breakpoint registers 29a and 29b, and the like.

As shown in FIG. 3, the ICE circuit 20 includes a write control means, first and second stop control means, an ICE control circuit section 37 as a switching control means and a function stop means, an interface circuit section 38, and a data format. It is configured to include a shift register 39 as a conversion means, a break determination comparator 40, and the like. The shift register 39 connects to the data trace register 2 via the ICE internal bus 41.
6a to 26h, an instruction decoder 31, and a program counter 36. And shift register 3
9 is any one of the data trace registers 26a to 26h, the instruction decoder 31, or the program counter 36;
The plurality of bits of parallel signal data inputted from the interface circuit section 38 is converted into 2-bit serial signal data based on the shift clock CK from the interface circuit section 38, and is output to the interface circuit section 38. or,
The shift register 39 converts the 2-bit serial signal data from the interface circuit section 38 into parallel signal data based on the shift clock CK, and transfers the data trace registers 26a to 26h, the instruction decoder 31,
Alternatively, it is output to one of the program counters 36.

A break judgment comparator 40 compares each program stop address stored in the breakpoint registers 29a and 29b with the program counter (PC
) 36, and when this count value reaches the program stop address of the breakpoint register 29a or 29b, a break control signal BC1 is output to the ICE control circuit section 37.

The ICE circuit 20 also includes an ICE control circuit section 3.
7, serial interface ports 43 and 44 for data transfer, and serial interface ports 45 for status transfer provided in the interface circuit section 38.
47 and six serial interface ports (hereinafter referred to as
It is connected to the ICE main body 13 via a port (simply referred to as a port).

A modulation circuit 48 is provided in the interface circuit section 38 in correspondence with the status transfer port 45, and the modulation circuit 48 controls the control circuit based on the clock signal of the DSP 11 generated by the clock generation section 35. 1 bit of the status signal ST from 32 is encoded. On the other hand, the ICE main body 13 has a
As shown in FIG. 2, a decoder 49 is provided corresponding to the status transfer port 45, and a clock extractor 5
0 is set. The clock extraction unit 50 receives the 1-bit status signal ST encoded by the modulation circuit 48.
A clock signal is extracted from the control circuit 51 and output to the control circuit 51. When this clock signal becomes stable, the control circuit 51 controls all ports 42 to 42 in synchronization with this clock.
Data communication is performed with the ICE circuit 20 via 47.

In order to establish synchronization with the ICE main body 13, the ICE circuit 20 repeatedly sends a data pattern that is easy to synchronize according to the encoding method at the start of communication. Then, after a certain period of time, the ICE circuit 20 changes the port that is transmitting data through normal serial communication without encoding, for example the status transfer port 46, from "H" to "
When the output level of the status transfer port 47 reaches a predetermined value, the ICE main unit 13 confirms that synchronization has been completed. It has become.

When the ICE circuit 20 is connected to the ICE main body 13 and a reset signal is input from the ICE main body 13 to the control circuit 32, the state shown in FIG.
As shown in a), the ICE circuit 20 becomes a reset input, only the break and data transfer ports 42 and 43 are in the input state, and the other ports 44 to 47 are in the L level output state. In this state, the ICE circuit 20 controls the IC according to the combination of signal values input from the ICE main body 13 to the break and data transfer ports 42 and 43.
The mode is E-stop mode, trace mode, ICE mode, or write mode.

That is, in the state shown in FIG. 4(a), when the combination of signal values of the break and data transfer ports 42 and 43 becomes "L, L", the ICE is activated as shown in FIG. 4(b). It enters stop mode. In this ICE stop mode, all ports 42 to 47 are in the input state, and "0" is input to the ICE circuit 20 by a pull-down resistor (not shown) provided inside the ICE circuit 20. As a result, the function of the ICE circuit 20 is stopped and the DSP 11 returns to normal operation.

In the state shown in FIG. 4(a), when the combination of signal values of the break and data transfer ports 42 and 43 becomes "L, H", the trace mode is activated as shown in FIG. 4(c). Become. In this trace mode, only the break port 42 is in the input state, and the other ports 43 to 4 are in the input state.
7 is in the output state. In addition, in the state shown in FIG. 4(a), when the combination of signal values of the break and data transfer ports 42 and 43 becomes "H, L", the ICE mode is entered as shown in FIG. 4(d). . In this ICE mode, the break port 42 is in the input state, and the status transfer ports 45 to 47 are in the output state. Further, in the ICE mode, the data transfer ports 43 and 44 are in a bus state in which input and output are possible.

Furthermore, in the state shown in FIG. 4(a), when the combination of signal values of the break and data transfer ports 42 and 43 becomes "H, H", a write operation is performed as shown in FIG. 4(e). mode. In this write mode, the break and data transfer ports 42 and 43 are in an input state, the status transfer ports 45 to 47 are in an L level output state, and a write voltage is applied to the data transfer port 44.

In the trace mode shown in FIG. 4(c), the interface circuit section 38 outputs the multi-bit status signal ST inputted from the control circuit 32 to the ICE main body 13 via the status transfer ports 45 to 47. It looks like this. In addition, in this trace mode, the program execution address is input from the program counter 36 to the shift register 39, and the interface circuit unit 38 outputs a shift clock CK to the shift register 39 and inputs 2-bit serial signal data. , and is output to the ICE main body 13 via data transfer ports 43 and 44.

In this trace mode, the trace program stored in the EPROM 21 is executed by the instruction decoder 31, and eight consecutive pieces of data in the RAM 22 or 23 are stored in the data trace registers 26a to 26.
26h, the ICE control circuit unit 37 adds an identification code ATR to each data in the data trace registers 26a to 26h based on the data storage signal DS from the address calculation unit 34, and sequentially stores the data in the shift register 3.
Transfer to 9. Then, the interface circuit section 38 outputs the shift clock CK and inputs the shift clock CK from the shift register 39 to 2.
Bit serial signal data is input and output to the ICE main body 13 via data transfer ports 43 and 44 to perform data tracing. Therefore, during this data tracing, the execution address of the program is not traced.

Furthermore, in the trace mode, the break control signal BC1 is input from the break judgment comparator 40 to the ICE control circuit section 37, or the ICE main body 1
When the break control signal BC2 is input from the break port 42 from the break port 42, the ICE control circuit section 37
Put the circuit 20 into ICE mode. IC shown in Figure 4(d)
In the E mode, the ICE control circuit unit 37 outputs a break signal SB to the control circuit 32 to stop the control circuit 32, instruction decoder 31, arithmetic unit 33, and address arithmetic unit 34.

Furthermore, the ICE control circuit unit 37 transfers the current execution address of the program counter 36 to the shift register 39 via the ICE internal bus 41, and the interface circuit unit 38 transfers the current execution address of the program counter 36 to the shift register 39 based on the shift clock CK. The execution address is saved in the memory 52 of the ICE main body 13 via the data transfer ports 43 and 44. or,
The ICE control circuit unit 37 stores the contents of the status register 33a at that time in, for example, the data trace register 26a via the data bus 30, and then stores the contents of the status register 33a at that time in the data trace register 26a.
The contents of a are transferred to the shift register 39 via the ICE internal bus 41. The interface circuit section 38 saves the contents of the status register 33a to the memory 52 of the ICE main body 13 via the data transfer ports 43 and 44 based on the shift clock CK.

Next, the ICE control circuit section 37 inputs the start address of the monitor program in the memory 52 provided in the ICE main body 13 via the data transfer ports 43 and 44, and converts it into parallel signal data in the shift register 39. After converting and storing in the program counter 36, C
Release the stoppage of PU17. As a result, the count value of the program counter 36 is transferred to the ICE main body 13 via the shift register 39 and the data transfer ports 43 and 44, and the monitor program in the memory 52 is read out. The program data read from the memory 52 is transferred to the instruction decoder 31 via the data transfer ports 43 and 44 and the shift register 39, decoded, and executed by the arithmetic unit 33.

Therefore, in this ICE mode, D
SP11 is placed under the control of external ICE device 15. That is, by operating the keyboard of the terminal computer 14,
By transferring a command for controlling the CE control circuit unit 37 to the control register 27 via the data transfer ports 43 and 44, the shift register 39, the data trace register 26a, and the data bus 30, the ICE
It becomes possible to control the CPU 17 by the control circuit section 37, and it becomes possible to perform necessary debugging.

To cancel the ICE mode, operate the keyboard of the terminal personal computer 14 and store a cancellation command in the control register 27, and then the ICE control circuit section 37 outputs a break signal SB to the control circuit 32 to control the ICE mode. The circuit 32, instruction decoder 31, arithmetic unit 33, and address arithmetic unit 34 are brought to a halt state. Next, I
The CE control circuit unit 37 inputs the execution address of the program counter 36 saved in the memory 52 via the data transfer ports 43 and 44, converts it into parallel signal data in the shift register 39, and transfers the execution address to the program counter 36.
Store in. Further, the ICE control circuit section 37 is connected to the memory 5.
The contents of the status register 33a saved in 2 are input via the data transfer ports 43 and 44, converted into parallel signal data by the shift register 39, and stored in the data trace register 26a.
The contents of are stored in the status register 33a via the data bus 33a.

After that, the ICE control circuit section 37 outputs a release signal to the control circuit 32 to release the stoppage of the CPU 17. Thereby, the program access of the CPU 17 is transferred to the EPROM 21, and the DSP 11 executes the original operation based on the program in the EPROM 21. Furthermore, Figure 4
In the write mode shown in FIG.
3 is stopped. Then, address data is inputted from the external ICE device 15 via the data transfer ports 43 and 44, converted into parallel signal data by the shift register 39, stored in the program counter 36, and sent to the EPRO.
Access the predetermined address of M21.

After that, program data is inputted from the external ICE device 15 through the data transfer ports 43 and 44, converted into parallel signal data by the shift register 39, and sent to one of the data trace registers 26a to 26h. It is output to the data bus 30 via the data bus 30. Then, when a write voltage is applied from the external ICE device 15 to the data transfer port 44, program data is written to a predetermined address of the EPROM 21. By repeatedly executing the above process, the contents of the EPROM 21 are rewritten.

In this way, in this embodiment, the ICE main body 13
When a reset signal is input to the control circuit 32 from the ICE main body 13 and only the break and data transfer ports 42 and 43 are in the input state, and the other ports 43 to 47 are in the L level output state, the break signal is input from the ICE main body 13 to the control circuit 32. The ICE circuit 20 is set to one of the following modes: ICE stop mode, trace mode, ICE mode, or write mode, depending on the combination of signal values input to the data transfer ports 42 and 43. In the write mode, the control circuit 32, instruction decoder 31, and arithmetic unit 33 are stopped, and address data and program data are input from the external ICE device 15 through the data transfer ports 43, 44 and the shift register 39. ,
Store the address data in the program counter 36 and
Since a predetermined address of the PROM 21 is accessed and a write voltage is applied to the data transfer port 44, the E formed in the DSP 11 by the ICE circuit 20 is
The contents of PROM 21 can be rewritten.

Furthermore, in this embodiment, the ICE circuit 20 is provided with a shift register 39 for converting parallel signal data into serial signal data, and the data transfer ports are serial interface ports 42 to 47, so data can be transferred in parallel. It is possible to reduce the number of ports allocated to the ICE circuit compared to the conventional ICE circuit.

Further, in this embodiment, the ICE circuit 20 receives a status signal S based on a clock signal for synchronization.
Since a modulation circuit 48 is provided to encode one bit of T,
There is no need to provide a port used only for synchronization,
The number of ports allocated to the ICE circuit 20 can be reduced more reliably. Further, in this embodiment, the ICE circuit 20 is
A plurality of data trace registers 26a to 26h are provided to trace the data stored in M22 and M23, and during data tracing, eight pieces of data are stored in each register 26a to 26h at a time and identification codes are sequentially added. Since the data is output as follows, multiple pieces of data can be traced almost simultaneously.

Further, in this embodiment, in the ICE stop mode, all ports 42 to 47 of all ICE circuits 20 are in the input state, and "0" is input to the ICE circuit 20 by a pull-down resistor (not shown) provided inside the ICE circuit 20. The system will stop functioning. This can prevent the ICE circuit 20 from interfering with the operation of the DSP 11 when it is not in use.

Furthermore, in this embodiment, the ICE of the ICE circuit 20
In this mode, the control circuit 32, instruction decoder 31, arithmetic unit 33, and address arithmetic unit 34 are temporarily stopped, and the execution address of the program counter 36 and the contents of the status register 33a at that time are
After saving the monitor program to the memory 52 of the CE main body 13 and storing the address of the monitor program in the memory 52 in the program counter 36, the stoppage of the CPU 17 is released, so the DSP 11 can be placed under the control of the external ICE device 15. It becomes possible to perform necessary debugging by operating the terminal personal computer 14.

Note that the state setting of each serial interface port 42 to 47 for transitioning the ICE circuit 20 from the reset state to the ICE stop mode, trace mode, ICE mode, or write mode is limited to the above embodiment. It is not a complete set of guidelines and can be modified and implemented as desired.

[0048]

[Effects of the Invention] As detailed above, according to the first invention,
In a semiconductor integrated circuit device in which a programmable nonvolatile memory is formed on a chip, the contents of the nonvolatile memory can be changed by an ICE circuit formed on the chip. In addition, the present invention can trace the execution address of a program, and can also trace the execution address of a program.
Data tracing can be performed.

The ICE circuit also includes a data format conversion means for converting parallel signal data within the semiconductor integrated circuit device into a plurality of serial signal data, and a data format conversion means for converting the serial signal data converted by the data format conversion means to an external ICE device. By providing a plurality of output serial interface ports, the number of ports allocated to the ICE circuit can be reduced compared to a device that transfers data in parallel.

Furthermore, by providing the ICE circuit with a modulation circuit that encodes the serial signal data of any one serial interface port based on a clock signal for synchronizing with an external ICE device, synchronization can be achieved. There is no need to provide a port for the ICE circuit, and the number of ports allocated to the ICE circuit can be reduced more reliably. Also, ICE
Since the circuit is provided with a plurality of registers for tracing data stored in the RAM, a plurality of data can be traced almost simultaneously.

The ICE circuit also includes a second stop control means for stopping the operation of the central processing unit according to a program in the nonvolatile memory based on a break control signal from an external ICE device; By including a switching control means for switching the operation of the central processing unit to the operation according to the monitor program of the external ICE device based on the stoppage of the operation of the processing unit, the central processing unit can be switched to an arbitrary address in the non-volatile memory. It becomes possible to place it under the control of an external ICE device.

Furthermore, by providing the ICE circuit with a function stop means for stopping the function of the ICE circuit based on a function stop signal from an external ICE device, the ICE circuit can be
When the circuit is not in use, it is possible to prevent interference with the operation of the semiconductor integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a schematic configuration diagram showing an example in which the present invention is embodied in a DSP.

FIG. 3 is a block circuit diagram showing details of a DSP in one embodiment.

4(a) is a diagram showing the attributes of each port in reset state, (b) is a diagram showing the attributes of each port in ICE stop mode, (c) is a diagram showing the attributes of each port in trace mode, (d) is a diagram showing the attributes of each port in ICE mode, (
e) is a diagram showing the attributes of each port in write mode.

FIG. 5 is a diagram showing the connection between the ICE circuit and the ICE main body.

[Explanation of symbols]

1 Nonvolatile memory 2 Central processing unit 2a Address generation circuit 2b Program counter 2c Program execution section 3, 22, 23 RAM 4 ICE circuit 5 First stop control means 6 Write control means 13 ICE main body 15 External ICE devices 26a to 26h Data Trace register 37
ICE control circuit unit 39 as a write control means, first and second stop control means, switching control means, and function stop means
Shift registers 42 to 4 as data format conversion means
7 Serial interface port 48 Modulation circuit 52 Memory

Claims (6)

[Claims] 1. A non-volatile memory (1) in which a program can be rewritten, an address generation circuit (2a) including a program counter (2b) for accessing a predetermined address of the non-volatile memory (1), and a read program. A central processing unit (2) equipped with a program execution unit (2c) that executes data at high speed, a RAM (3) that stores data used for program execution, and a central processing unit (
2) ICE that controls and monitors the operation based on external commands.
(in-circuit emulator) circuit (4) formed on one semiconductor chip, the ICE circuit (4) is configured to program the program based on a write control signal input from an external ICE device. Execution part (2
a first stop control means (5) for stopping the operation of b);
Address data input from an external ICE device is input to the address generation circuit (2a),
) Write control means (6) writes program data to a predetermined address of the nonvolatile memory (1) accessed by
) A semiconductor integrated circuit device characterized by comprising: 2. The ICE circuit (4) includes a data format conversion means (39) for inputting parallel signal data in a semiconductor integrated circuit device and converting it into serial signal data; 2. The device according to claim 1, further comprising a plurality of serial interface ports (42-47) for outputting the converted serial signal data and other status information of the central processing unit (2) to an external ICE device (15). semiconductor integrated circuit devices. [Claim 3] The ICE circuit (4) is an external ICE circuit.
The ICE circuit (4) is equipped with a synchronization clock generator for serial data transfer with the ICE main body (13) of the device (15), and the serial clock of any one serial interface port is provided based on the clock signal. It is equipped with a modulation circuit (48) that encodes signal data, and simultaneously transmits serial signal data and a synchronized clock to the ICE main body (
13) The semiconductor integrated circuit device according to claim 2, wherein 4. The ICE circuit (4) includes a RAM (2).
A data format conversion means (39) includes a plurality of registers (26a to 26h) for tracing the data stored in the registers (2, 23), and sequentially adds an identification code to the data in each register (26a to 26h). 3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is configured to transfer data to . 5. The ICE circuit (4) is an external ICE circuit.
The central processing unit (
2) second stop control means (
37), and the contents of the program counter (2b) and status register (33a) are stored in the memory in the ICE main body (13) based on the suspension of the operation of the central processing unit (2) by the second halt control means (37). After that,
Program access is switched from the non-volatile memory (1) to the memory of the ICE main body (13) and the central processing unit (
2. The semiconductor integrated circuit device according to claim 1, further comprising switching control means (37) for causing said external ICE device to execute a monitor program in said external ICE device. 6. The ICE circuit (4) is an external ICE circuit.
2. The semiconductor integrated circuit device according to claim 1, further comprising a function stop means (37) for stopping the function of the ICE circuit (4) based on a function stop signal from the device (15).